Cross-coupled transistor circuit defined on three gate electrode tracks

• US 10,651,200 B2
• Filed: 03/15/2013
• Issued: 05/12/2020
• Est. Priority Date: 03/13/2008
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Tela Innovations, Inc.
• Inventors: Becker, Scott T., Mali, Jim, Lambert, Carole
• Primary Examiner(s): Sandvik, Benjamin P
• Application Number:
  US13/831,605
• Publication Number:
  US 20130200464A1
• Time in Patent Office: 2,615 Days
• Field of Search: None
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2027/11853 Sub-micron technology
• CPC Class Codes: H01L 2027/11875 Wiring region, routing
• CPC Class Codes: H01L 2027/11887 Three levels of metal
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/49844 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/10 SRAM devices comprising bipolar components
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

Claims

1. A cross-coupled transistor circuit, comprising:

a first PMOS transistor formed in part by a first gate electrode;

a second PMOS transistor formed in part by a second gate electrode;

a first NMOS transistor formed in part by a third gate electrode co-aligned with the second gate electrode;

a second NMOS transistor formed in part by a fourth gate electrode,

wherein the gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node,

wherein the gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node, and

wherein each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

2. A cross-coupled transistor circuit as recited in claim 1, wherein the first PMOS transistor is positioned next to the second PMOS transistor.

3. A cross-coupled transistor circuit as recited in claim 1, wherein the first NMOS transistor is positioned next to the second NMOS transistor.

4. A cross-coupled transistor circuit as recited in claim 1, wherein each of the first, second, and third gate electrodes extend in a first direction.

5. A cross-coupled transistor circuit as recited in claim 4, wherein a distance between the gate electrodes of the first and second PMOS transistors as measured in a second direction is greater than a distance between the gate electrodes of the first and second NMOS transistors as measured in the second direction, the second direction perpendicular to the first direction.

6. A cross-coupled transistor circuit as recited in claim 4, wherein a distance between the gate electrodes of the first and second NMOS transistors as measured in a second direction is greater than a distance between the gate electrodes of the first and second PMOS transistors as measured in the second direction, the second direction perpendicular to the first direction.

7. A cross-coupled transistor circuit as recited in claim 4, wherein the first gate electrode is positioned a gate pitch distance away from the third gate electrode, the gate pitch distance measured in a second direction perpendicular to the first direction.

8. A cross-coupled transistor circuit as recited in claim 7, wherein a distance between a centerline of the first gate electrode and a centerline of the second gate electrode as measured in the second direction is a multiple of the gate pitch distance.

9. A cross-coupled transistor circuit as recited in claim 8, wherein the multiple of the gate pitch distance is an integer multiple.

10. A cross-coupled transistor circuit as recited in claim 4, wherein the gate electrode of the first PMOS transistor has at least one end substantially aligned in the first direction with at least one end of the gate electrode of the second PMOS transistor.

11. A cross-coupled transistor circuit as recited in claim 4, wherein the gate electrode of the first PMOS transistor has a first end substantially aligned in the first direction with a first end of the gate electrode of the second PMOS transistor, and wherein the gate electrode of the first PMOS transistor has a second end substantially aligned in the first direction with a second end of the gate electrode of the second PMOS transistor.

12. A cross-coupled transistor circuit as recited in claim 10, wherein the gate electrode of the first NMOS transistor has at least one end substantially aligned in the first direction with at least one end of the gate electrode of the second NMOS transistor.

13. A cross-coupled transistor circuit as recited in claim 4, wherein the gate electrode of the first NMOS transistor has a first end substantially aligned in the first direction with a first end of the gate electrode of the second NMOS transistor, and wherein the gate electrode of the first NMOS transistor has a second end substantially aligned in the first direction with a second end of the gate electrode of the second NMOS transistor.

14. A cross-coupled transistor circuit as recited in claim 4, wherein the gate electrode of the first PMOS transistor has at least one end substantially aligned in the first direction with at least one end of the gate electrode of the second PMOS transistor, wherein the gate electrode of the first NMOS transistor has at least one end substantially aligned in the first direction with at least one end of the gate electrode of the second NMOS transistor.

15. A cross-coupled transistor circuit as recited in claim 4, wherein the gate electrode of the first PMOS transistor has at least one end substantially aligned in the first direction with at least one end of the gate electrode of the second PMOS transistor, wherein the gate electrode of the first NMOS transistor has a first end substantially aligned in the first direction with a first end of the gate electrode of the second NMOS transistor, and wherein the gate electrode of the first NMOS transistor has a second end substantially aligned in the first direction with a second end of the gate electrode of the second NMOS transistor.

16. A cross-coupled transistor circuit as recited in claim 4, wherein the gate electrode of the first PMOS transistor has a first end substantially aligned in the first direction with a first end of the gate electrode of the second PMOS transistor, and wherein the gate electrode of the first PMOS transistor has a second end substantially aligned in the first direction with a second end of the gate electrode of the second PMOS transistor, wherein the gate electrode of the first NMOS transistor has at least one end substantially aligned in the first direction with at least one end of the gate electrode of the second NMOS transistor.

17. A cross-coupled transistor circuit as recited in claim 4, wherein the gate electrode of the first PMOS transistor has a first end substantially aligned in the first direction with a first end of the gate electrode of the second PMOS transistor, and wherein the gate electrode of the first PMOS transistor has a second end substantially aligned in the first direction with a second end of the gate electrode of the second PMOS transistor, wherein the gate electrode of the first NMOS transistor has a first end substantially aligned in the first direction with a first end of the gate electrode of the second NMOS transistor, and wherein the gate electrode of the first NMOS transistor has a second end substantially aligned in the first direction with a second end of the gate electrode of the second NMOS transistor.

18. A cross-coupled transistor circuit as recited in claim 1, wherein the first and second PMOS transistors are collectively separated from the first and second NMOS transistors by an inner region, wherein the gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to each other through a first set of one or more conductive structures positioned within the inner region.

19. A cross-coupled transistor circuit as recited in claim 18, wherein the gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to each other through a second set of one or more conductive structures positioned within the inner region, the second set of one or more conductive structures exclusive of the first set of one or more conductive structures.

20. A cross-coupled transistor circuit, comprising:

a first PMOS transistor having a gate electrode formed by a first conductive structure;

a second PMOS transistor having a gate electrode formed by a second conductive structure;

a first NMOS transistor having a gate electrode formed by a third conductive structure;

a second NMOS transistor having a gate electrode formed by a fourth conductive structure,

wherein at least one of the first and second conductive structures forms only one transistor gate electrode,

wherein at least one of the third and fourth conductive structures forms only one transistor gate electrode,

each of the first and second PMOS transistors having a respective gate electrode electrically connected to a gate electrode of a different one of the first and second NMOS transistors,

each of the first and second PMOS transistors and the first and second NMOS transistors having a respective diffusion terminal electrically connected to each other through at least one overlying conductive structure.

21. A cross-coupled transistor circuit, comprising:

a first PMOS transistor having a gate electrode formed by a first conductive structure;

a second PMOS transistor having a gate electrode formed by a second conductive structure;

a first NMOS transistor having a gate electrode formed by a third conductive structure;

a second NMOS transistor having a gate electrode formed by a fourth conductive structure,

wherein at least one of the first and second conductive structures forms only one transistor gate electrode,

wherein at least one of the third and fourth conductive structures forms only one transistor gate electrode,

each of the first and second PMOS transistors having a respective gate electrode electrically connected to a gate electrode of a different one of the first and second NMOS transistors,

each of the first and second PMOS transistors and the first and second NMOS transistors having a respective diffusion terminal electrically connected to each other,

the gate electrodes of the second PMOS transistor and first NMOS transistor positioned along a same line.

22. A cross-coupled transistor circuit as recited in claim 21, wherein the gate electrodes of the first PMOS transistor and second NMOS transistor are positioned along different lines.

23. A cross-coupled transistor circuit as recited in claim 21, wherein the gate electrode of the second PMOS transistor is linear-shaped and has a lengthwise oriented centerline, and wherein the gate electrode of the first NMOS transistor is linear-shaped and has a lengthwise oriented centerline.

24. A cross-coupled transistor circuit as recited in claim 23, wherein the same line along which the gate electrodes of the second PMOS transistor and first NMOS transistor are positioned is aligned with the lengthwise oriented centerlines of both the second PMOS transistor and the first NMOS transistor.

25. A cross-coupled transistor circuit as recited in claim 24, wherein the gate electrodes of the first PMOS transistor and second NMOS transistor are positioned along different lines.

26. A semiconductor chip, comprising:

a first transistor of a first transistor type having a gate electrode formed to extend in a substantially straight manner in a first direction;

a second transistor of the first transistor type having a gate electrode formed to extend in a substantially straight manner in the first direction;

a first transistor of a second transistor type having a gate electrode formed to extend in a substantially straight manner in the first direction; and

a second transistor of the second transistor type having a gate electrode formed to extend in a substantially straight manner in the first direction,

wherein the first transistor of the first transistor type and the second transistor of the first transistor type share a first diffusion region of a first diffusion type,

wherein the first transistor of the second transistor type includes a first diffusion region of a second diffusion type,

wherein the second transistor of the second transistor type includes a second diffusion region of the second diffusion type, and

wherein the first diffusion region of the second diffusion type is physically separate from the second diffusion region of the second diffusion type by an intervening non-active region, and

wherein the gate electrode of the first transistor of the first transistor type is formed by a linear-shaped conductive structure that is aligned in the first direction with the intervening non- active region that physically separates the first diffusion region of the second diffusion type from the second diffusion region of the second diffusion type.

27. A semiconductor chip as recited in claim 26, wherein both the gate electrode of the second transistor of the first transistor type and the gate electrode of the second transistor of the second transistor type are positioned along a same line oriented in the first direction.

28. A semiconductor chip as recited in claim 27, wherein the gate electrode of the second transistor of the first transistor type is physically separate from the gate electrode of the second transistor of the second transistor type.

29. A semiconductor chip as recited in claim 28, further comprising:

a first conductive structure formed within a higher interconnect level of the chip relative to a gate electrode level of the chip,

wherein the first diffusion region of the second diffusion type is electrically connected to the second diffusion region of the second diffusion type through the first conductive structure formed within the higher interconnect level of the chip.

30. A semiconductor chip as recited in claim 28, further comprising:

a first conductive structure formed within a higher interconnect level of the chip relative to a gate electrode level of the chip,

wherein the first diffusion region of the second diffusion type and the second diffusion region of the second diffusion type and the first diffusion region of the first diffusion type are electrically connected to each other through the first conductive structure formed within the higher interconnect level of the chip.

31. A semiconductor chip as recited in claim 30, further comprising:

a second conductive structure formed within a higher interconnect level of the chip relative to the gate electrode level of the chip,

wherein the gate electrode of the first transistor of the first transistor type is electrically connected to the gate electrode of the second transistor of the second transistor type through the second conductive structure.

32. A semiconductor chip as recited in claim 31, further comprising:

a third conductive structure formed within a higher interconnect level of the chip relative to the gate electrode level of the chip,

wherein the gate electrode of the second transistor of the first transistor type is electrically connected to the gate electrode of the first transistor of the second transistor type through the third conductive structure.

33. A semiconductor chip as recited in claim 26, wherein the gate electrode of the first transistor of the first transistor type extends through the intervening non-active region that physically separates the first diffusion region of the second diffusion type from the second diffusion region of the second diffusion type.

34. A semiconductor chip, comprising:

a first transistor of a first transistor type having a gate electrode formed from a portion of a first substantially rectangular-shaped conductive structure;

a second transistor of the first transistor type having a gate electrode formed from a portion of a second substantially rectangular-shaped conductive structure;

a first transistor of a second transistor type having a gate electrode formed from a portion of a third substantially rectangular-shaped conductive structure; and

a second transistor of the second transistor type having a gate electrode formed from a portion of a fourth substantially rectangular-shaped conductive structure,

the gate electrode of the first transistor of the first transistor type electrically connected to the gate electrode of the second transistor of the second transistor type,

the gate electrode of the second transistor of the first transistor type electrically connected to the gate electrode of the first transistor of the second transistor type,

the gate electrodes of the first and second transistors of the first transistor type having respective lengthwise centerlines separated by a gate pitch,

the gate electrodes of the first and second transistors of the second transistor type having respective lengthwise centerlines separated by more than the gate pitch.

35. A semiconductor chip as recited in claim 34, further comprising:

an interconnect level conductive structure formed to extend from a location overlying the second substantially rectangular-shaped conductive structure to a location overlying the third substantially rectangular-shaped conductive structure.

36. A semiconductor chip as recited in claim 35, wherein the interconnect level conductive structure includes at least one turn in a horizontal plane that is substantially parallel to a substrate of the semiconductor chip.

37. A semiconductor chip as recited in claim 35, wherein the interconnect level conductive structure is a first interconnect level conductive structure, the semiconductor chip including a second interconnect level conductive structure formed to extend from a location overlying the first substantially rectangular-shaped conductive structure to a location overlying the fourth substantially rectangular-shaped conductive structure.

38. A semiconductor chip as recited in claim 37, wherein the second interconnect level conductive structure includes at least two turns in a horizontal plane that is substantially parallel to a substrate of the semiconductor chip.

39. A semiconductor chip as recited in claim 37, wherein the first and second interconnect level conductive structures are formed in a same interconnect level of the semiconductor chip.