Method for static gate clamping in multi-output gate driver systems

• US 10,651,723 B1
• Filed: 10/22/2018
• Issued: 05/12/2020
• Est. Priority Date: 10/22/2018
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Frank, Wolfgang, Fabbro, Simone, Norling, Karl
• Primary Examiner(s): Skibinski, Tomi
• Application Number:
  US16/166,953
• Publication Number:
  US 20200127552A1
• Time in Patent Office: 568 Days
• Field of Search: 327108-112, 327427, 327434, 327437, 326 82, 326 83, 326 87
• CPC Class Codes: H02M 1/096 the power supply of the control circuit being connected in parallel to the main switching element H02M1/092 takes precedence
• CPC Class Codes: H03K 17/163 Soft switching
• CPC Class Codes: H03K 17/168 in composite switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/17772 for powering on or off

Abstract

A multi-output gate driver system comprises a power device having a gate node; a first driver having an input and an output coupled to the gate node; a second driver having an input and an output coupled to the gate node; a first comparator having a first input coupled to the output of the second driver, a second input coupled to a first reference voltage, and an output; a second comparator having a first input coupled to the output of the second driver, a second input coupled to a second reference voltage, and an output; and a logic circuit having an input for receiving a control signal, a first output coupled to the input of the first driver, and a second output coupled to the input of the second driver.

Claims

1. A multi-output gate driver system comprising:

a power device having a gate node;

a first driver having an input and an output coupled to the gate node for actively switching the power device on and off;

a second driver having an input and an output coupled to the gate node;

a first comparator having a first input coupled to the output of the second driver, a second input coupled to a first reference voltage, and an output;

a second comparator having a first input coupled to the output of the second driver, a second input coupled to a second reference voltage, and an output; and

a logic circuit having a first input for receiving a control signal for switching the power device on and off, a second input coupled to the outputs of the first and second comparators, a first output coupled to the input of the first driver, and a second output coupled to the input of the second driver,

wherein a signal on the second input of the logic circuit indicates whether the output of the second driver reaches or exceeds the first reference voltage or whether the output of the second driver reaches or falls below the second reference voltage, wherein the output of the second driver is configured to be correspondingly clamped to either a positive voltage rail or a negative voltage rail in response to a signal on the second output of the logic circuit, and wherein the second driver is selectively configured to be in a high impedance state depending upon a logic state of the logic circuit.

2. The multi-output gate driver system of claim 1, wherein the second driver is configured to be clamped during both a turn-on mode of operation and a turn-off mode of operation.

3. The multi-output gate driver system of claim 1, wherein the second driver is configured to be clamped during a turn-on mode of operation and configured to actively switch during a turn-off mode of operation.

4. The multi-output gate driver system of claim 1, wherein the second driver is configured to be clamped during a turn-off mode of operation and configured to actively switch during a turn-on mode of operation.

5. The multi-output gate driver system of claim 1, wherein the second driver is configured to be clamped or actively switched in response to an additional control signal received by the logic circuit.

6. The multi-output gate driver system of claim 1, wherein the first and second comparators comprise at least one of an input filter or an output filter.

7. The multi-output gate driver system of claim 1, further comprising a first gate resistor coupled between the output of the first driver and the gate node of the power device.

8. The multi-output gate driver system of claim 7, further comprising a second gate resistor coupled between the output of the second driver and the gate node of the power device.

9. A method for operating a multi-output gate driver system including first and second gate drivers each including an output coupled to a power device, the method comprising:

turning on the power device with the first gate driver output, sensing a voltage of the second gate driver output to determine that the voltage at the second gate driver output is greater than a first reference voltage, and clamping the voltage of the second gate driver output to a first clamping voltage in a first mode of operation;

turning off the power device with the first gate driver output, sensing the voltage of the second gate driver output to determine that the voltage at the second gate driver output is less than a second reference voltage, and clamping the voltage of the second gate driver output to a second clamping voltage in a second mode of operation;

sensing the second gate driver output with first and second comparators in the first mode of operation;

sensing the second gate driver output with first and second comparators in the second mode of operation; and

selectively placing the second driver in a high impedance state depending upon a logic state of the first and second comparators, and a logic state of an input signal of the multi-output gate driver system.

10. The method of claim 9, wherein the second gate driver is delayed with respect to the first gate driver in the first mode of operation.

11. The method of claim 9, wherein the second gate driver is delayed with respect to the first gate driver in the second mode of operation.

12. The method of claim 9, further comprising coupling at least one of a first gate resistor between the first gate driver and the power device, and a second gate resistor between the second gate driver and the power device.

13. A method of operating a multi-output gate driver system comprising a power device having a gate node, the method comprising:

actively switching the power device on and off with a first driver coupled to the gate node;

selectively driving the gate node with a second driver;

comparing an output of the second driver to a first reference voltage to generate a first logic signal;

comparing the output of the second driver to a second reference voltage to generate a second logic signal;

logically combining a control signal of the multi-output gate driver system, the first logic signal, and the second logic signal to generate an output logic signal;

clamping the output of the second driver to either a positive voltage rail or a negative voltage rail in response to the output logic signal; and

selectively placing the second driver in a high impedance state in response to the output logic signal.

14. The method of claim 13, wherein the second driver is clamped during both a turn-on mode of operation and a turn-off mode of operation.

15. The method of claim 13, wherein the second driver is clamped during a turn-on mode of operation and actively switched during a turn-off mode of operation.

16. The method of claim 13, wherein the second driver is clamped during a turn-off mode of operation and actively switched during a turn-on mode of operation.

17. The method of claim 13, wherein the second driver is clamped or actively switched in response to logically combining an additional control signal with the control signal of the multi-output gate driver system, the first logic signal, and the second logic signal to generate the output logic signal.

18. The method of claim 13, further comprising filtering the first and second logic signals.

19. The method of claim 13, further comprising coupling a first gate resistor between the output of the first driver and the gate node of the power device.

20. The method of claim 19, further comprising coupling a second gate resistor between the output of the second driver and the gate node of the power device.