Flip-flop and semiconductor system including the same

• US 10,651,828 B2
• Filed: 06/15/2017
• Issued: 05/12/2020
• Est. Priority Date: 10/31/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hwang, Hyun-Chul, Kim, Ah-Reum, Kim, Min-Su
• Primary Examiner(s): Donovan, Lincoln D
• Assistant Examiner(s): Cheng, Diana J.
• Application Number:
  US15/623,412
• Publication Number:
  US 20180123569A1
• Time in Patent Office: 1,062 Days
• CPC Class Codes: H03K 19/21 EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence
• CPC Class Codes: H03K 3/356121 with synchronous operation H03K3/35613, H03K3/356147 take precedence
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors

Abstract

A flip-flop generates a first feedback signal using a signal generated inside the flip-flop. The flip-flop includes a first stage circuit, a second stage circuit and a third stage circuit. The first stage circuit receives a first data signal and a clock signal and generates a first internal signal through a first node. The second stage circuit receives the first internal signal, the clock signal, and the first feedback signal and generates a second internal signal through a second node. The third stage circuit generates a second data signal by latching the second internal signal when the clock signal is at a first level, using the second internal signal and the clock signal. The second stage circuit cuts off at least one first current path between the second node and a power supply, based on the first feedback signal, when the clock signal is at a second level.

Claims

1. A flip-flop which generates a first feedback signal using a signal generated inside the flip-flop, the flip-flop comprising:

a first stage circuit that receives a first data signal and a clock signal and that generates a first internal signal through a first node;

a second stage circuit that receives the first internal signal, the clock signal, and the first feedback signal and that generates a second internal signal through a second node; and

a third stage circuit that generates a second data signal by latching the second internal signal when the clock signal is at a first level, using the second internal signal and the clock signal,

wherein the second stage circuit cuts off at least one first current path between the second node and a power supply, based on the first feedback signal, when the clock signal is at a second level, and

wherein the second stage circuit forms a second current path between the second node and the power supply, based on the first internal signal and the clock signal.

2. The flip-flop according to claim 1,

wherein the second stage circuit cuts off the at least one first current path and the second current path, such that the second node is kept discharged, when:

the second node is discharged;

the first internal signal is constant at one of the first level and the second level; and

the clock signal transits from the first level to the second level.

3. The flip-flop according to claim 2, wherein the second stage circuit forms the second current path, such that the second node is precharged by the second current path, when:

the second node is discharged;

the first internal signal is constant at the other one of the first level and the second level; and

the clock signal transits from the first level to the second level.

4. The flip-flop according to claim 1,

wherein the first feedback signal comprises a signal generated using the second internal signal.

5. The flip-flop according to claim 1, wherein the second stage circuit comprises:

a pull-up circuit connecting the power supply to the second node; and

a pull-down circuit connecting a ground to the second node, and

the pull-up circuit comprises;

at least one first PMOS transistor controlled to be turned on/off by receiving the clock signal;

at least one second PMOS transistor controlled to be turned on/off by receiving the first internal signal; and

at least one third PMOS transistor controlled to be turned on/off by receiving the first feedback signal, and

the pull-down circuit comprises;

at least one first NMOS transistor controlled to be turned on/off by receiving the clock signal;

at least one second NMOS transistor controlled to be turned on/off by receiving the first internal signal; and

at least one third NMOS transistor controlled to be turned on/off by receiving the first feedback signal.

6. The flip-flop according to claim 1,

wherein the second stage circuit comprises at least one switch device controlled to be turned on/off based on the first feedback signal, and cuts off the at least one first current path by turning off the switch device.

7. The flip-flop according to claim 1,

wherein the first stage circuit further receives a second feedback signal, comprises at least one switch device controlled to be turned on/off based on the second feedback signal, and controls the switch device such that the first node does not float by grounding the first node or connecting the first node to the power supply, based on the second feedback signal.

8. A flip-flop which generates a first feedback signal using a signal generated inside the flip-flop, the flip-flop comprising:

a first stage circuit that receives a first data signal and a clock signal and that generates a first internal signal through a first node;

a second stage circuit that receives the first internal signal, the clock signal, and the first feedback signal and that generates a second internal signal through a second node; and

a third stage circuit that generates a second data signal by latching the second internal signal when the clock signal is at a first level, using the second internal signal and the clock signal,

wherein the second stage circuit cuts off at least one first current path between the second node and a power supply, based on the first feedback signal, when the clock signal is at a second level, and

wherein the second stage circuit comprises;

a pull-up circuit connecting the power supply to the second node; and

a pull-down circuit connecting a ground to the second node,

the pull-up circuit comprises;

at least one first PMOS transistor controlled to be turned on/off by receiving the clock signal;

at least one second PMOS transistor controlled to be turned on/off by receiving the first internal signal; and

at least one third PMOS transistor controlled to be turned on/off by receiving the first feedback signal, and

the pull-down circuit comprises;

at least one first NMOS transistor controlled to be turned on/off by receiving the clock signal;

at least one second NMOS transistor controlled to be turned on/off by receiving the first internal signal; and

at least one third NMOS transistor controlled to be turned on/off by receiving the first feedback signal.

9. The flip-flop according to claim 8,

wherein the second stage circuit forms a second current path between the second node and the power supply, based on the first internal signal and the clock signal.

10. The flip-flop according to claim 9,

wherein the second stage circuit cuts off the at least one first current path and the second current path, such that the second node is kept discharged, when:

the second node is discharged;

the first internal signal is constant at one of the first level and the second level; and

the clock signal transits from the first level to the second level.

11. The flip-flop according to claim 10, wherein the second stage circuit forms the second current path, such that the second node is precharged by the second current path, when:

the second node is discharged;

the first internal signal is constant at the other one of the first level and the second level; and

the clock signal transits from the first level to the second level.

12. The flip-flop according to claim 8,

wherein the first feedback signal comprises a signal generated using the second internal signal.

13. The flip-flop according to claim 8,

wherein the second stage circuit cuts off the at least one first current path by turning off the at least one third PMOS transistor.

14. The flip-flop according to claim 8,

wherein the first stage circuit further receives a second feedback signal, comprises at least one switch device controlled to be turned on/off based on the second feedback signal, and controls the switch device such that the first node does not float by grounding the first node or connecting the first node to the power supply, based on the second feedback signal.