Mission critical wireless communication link master gateway

• US 10,652,059 B2
• Filed: 06/19/2019
• Issued: 05/12/2020
• Est. Priority Date: 06/19/2018
• Status: Active Grant

• Current Assignee: CoreTigo, Ltd.
• Original Assignee: CoreTigo, Ltd.
• Inventors: Blonskey, Ofer, Zigman, Eran, Wolberg, Dan
• Primary Examiner(s): Tran, Pablo N
• Application Number:
  US16/446,004
• Publication Number:
  US 20190386860A1
• Time in Patent Office: 328 Days
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04W 84/18 Self-organising networks, e.g. ad-hoc networks or sensor networks
• CPC Class Codes: H04W 88/08 Access point devices
• CPC Class Codes: H04W 88/16 Gateway arrangements

Abstract

A master gateway operable in a wireless system is provided. The master gateway includes a plurality of receivers configured to wirelessly communicate over the mission critical wireless link system with a plurality of devices; a processing circuitry coupled to the plurality of receivers; and a memory containing instructions that, when executed by the processing circuitry, configure the processing circuitry to at least control the operation of the plurality of receivers, such that at least one of the plurality of receivers is configured to receive a plurality of transmissions from the plurality of devices in succession wherein a guard time between transmissions is significantly smaller than a processing time of a receiver.

Claims

1. A method of receiving multiple packets in sequence, the method is performed by a receiver, comprising:

detecting a first packet;

decoding a first packet;

reconfiguring at least one component of the receiver when its operation on the decoded first packet is completed;

detecting a second packet; and

decoding a second packet with at least one reconfigured component, wherein a guard time between the first packet and second packet is substantially shorter than the receiver processing delay.

2. The method of claim 1, wherein reconfiguring the at least one component further comprises:

generating a reset signal.

3. The method of claim 1, wherein the method is repeated for a plurality packets received in a sequence.

4. The method according to claim 1, wherein decoding of any one of the first packet and the second packet further comprises at least one of:

Estimating and correcting a carrier frequency offset (CFO), performing an MLSE decoding, performing an AGC correction, and performing a digital down conversion.

5. The method according to claim 1, wherein decoding of any one of the first packet and the second packet is performed using a GFSK modulation.

6. The method of claim 1, wherein decoding of any one of the first packet and the second packet is performed using the IO-Link Wireless protocol.

7. The method of claim 1, wherein a reconfiguration time of any of the instances are determined by at least one of:

an external clock, a slot time generation, a comparison of a clock to an a-priory known protocol timing, and counting bits from the first bit to a known packet length.