System and method for routing-based internet security

• US 10,652,214 B2
• Filed: 08/17/2017
• Issued: 05/12/2020
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: May Patents Ltd.
• Original Assignee: May Patents Ltd.
• Inventors: Binder, Yehuda
• Primary Examiner(s): Sholeman, Abu S
• Application Number:
  US15/679,185
• Publication Number:
  US 20180270204A1
• Time in Patent Office: 999 Days
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G06F 21/80 in storage media based on magnetic or optical technology, e.g. disks with sectors preventing unauthorised reproduction or copying of disc-type recordable media G11B20/00
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: G06F 7/58 Random or pseudo-random number generators
• CPC Class Codes: H04L 51/046 Interoperability with other network applications or services
• CPC Class Codes: H04L 63/0281 Proxies
• CPC Class Codes: H04L 63/0428 wherein the data content is protected, e.g. by encrypting or encapsulating the payload
• CPC Class Codes: H04L 63/18 using different networks or channels, e.g. using out of band channels cryptographic mechanisms or cryptographic arrangements for key distribution involving distinctive intermediate devices or communication paths H04L9/0827; cryptographic mechanisms or cryptographic arrangements for authentication using a plurality of channels H04L9/3215
• CPC Class Codes: H04L 67/63 Routing a service request depending on the request content or context

Abstract

Method and system for improving the security of storing digital data in a memory or its delivery as a message over the Internet from a sender to a receiver using one or more hops is disclosed. The message is split at the sender into multiple overlapping or non-overlapping slices according to a slicing scheme, and the slices are encapsulated in packets each destined to a different relay server as an intermediate node according to a delivery scheme. The relay servers relay the received slices to another other relay server or to the receiver. Upon receiving all the packets containing all the slices, the receiver combines the slices reversing the slicing scheme, whereby reconstructing the message sent.

Claims

1. An apparatus for connecting to a processor in a first enclosure and to a location-addressable memory in a second enclosure having an address space, the memory is connectable to the processor via a bus of a first type that uses multiple wires or conductors, the apparatus comprising:

a first connector couplable to a first bus of said first type for connecting to said processor;

a first interface coupled to said first connector for receiving a first address word in said address space from said processor, the first address word consists of a sequence of bits, wherein each of the bits is associated with a level of significance;

a second connector couplable to a second bus that uses multiple wires or conductors for connecting to said memory;

a second interface coupled to said second connector for transmitting a second address word in said address space to said memory, the second address word consists of a sequence of bits, wherein each of the bits is associated with a level of significance;

a scrambler coupled between said first and second interfaces for converting using a one-to-one mapping said first address word to said second address word that is distinct from said first address word; and

a single enclosure housing said first and second connectors, said first and second interfaces, and said scrambler,

wherein the single enclosure is separate from, and external to, each of the first and second enclosures,

wherein said first bus is further carrying a power signal, and wherein the apparatus is powered only by the power signal.

2. The apparatus according to claim 1, wherein the converting is based on, or using, re-arranging the sequence of at least two bits in said first address word.

3. The apparatus according to claim 1, wherein the converting is based on, or using, changing the significance level of at least two bits in said first address word.

4. The apparatus according to claim 1, wherein said scrambler is based only on electrical connections.

5. The apparatus according to claim 1, wherein said scrambler is based on logic gates implementing a Boolean function.

6. The apparatus according to claim 5, wherein said scrambler is using, or is based on, Programmable Logic Device (PLD), a memory, or a processor.

7. The apparatus according to claim 1, wherein said conversion scheme is programmable.

8. The apparatus according to claim 7, wherein said converting scheme is programmable by the processor.

9. The apparatus according to claim 8, wherein said scrambler coupled to said first bus for being addressable by said processor.

10. The apparatus according to claim 1, wherein said second bus type is of the same type of said first bus.

11. The apparatus according to claim 1, wherein said second bus type is distinct from said first bus type.

12. The apparatus according to claim 1, wherein said memory is based on electrostatic, ferroelectric, magnetic, acoustic, optical, chemical, electronic, electric, or mechanical storage medium.

13. The apparatus according to claim 12, wherein said memory is file-addressable or content-addressable.

14. The apparatus according to claim 12, wherein said apparatus is part of a Network-attached Storage (NAS) or a Storage Area Network (SAN).

15. The apparatus according to claim 12, wherein said memory is a once written memory.

16. The apparatus according to claim 12, wherein said memory is connectable to said processor to be read from, or written to, via the second bus.

17. The apparatus according to claim 16, wherein said second bus is a parallel bus.

18. The apparatus according to claim 16, wherein said second bus is a bit-serial bus.

19. The apparatus according to claim 1, further comprising a power supply having a power port couplable to be powered from a power signal, said power supply having one or more Direct Current (DC) outputs for powering at least part of said memory.

20. The apparatus according to claim 1, wherein said memory is a sequential accessed memory, or wherein said memory is location-based, randomly-accessed, and can be written multiple times.

21. The apparatus according to claim 1, wherein said memory is based on semiconductor storage medium.

22. The apparatus according to claim 21, wherein said memory is volatile, and comprises one out of:

RAM, SRAM, DRAM, TTRAM and Z-RAM.

23. The apparatus according to claim 21, wherein said memory is non-volatile.

24. The apparatus according to claim 23, wherein said memory is one out of:

ROM, PROM, EPROM and EEROM, or is based on Flash technology.

25. The apparatus according to claim 23, wherein said memory is a SSD drive or USB ‘

Thumb’

drive.

26. The apparatus according to claim 1, wherein said memory is based on non-volatile magnetic storage medium.

27. The apparatus according to claim 26, wherein said memory is an Hard Disk Drive (HDD).

28. The apparatus according to claim 1, wherein said memory is based on an optical storage medium.

29. The apparatus according to claim 28, wherein said storage medium is recordable and removable, and wherein said memory includes an optical disk drive.

30. The apparatus according to claim 29, wherein said storage medium is one out of:

CD-RW, DVD-RW, DVD+RW, DVD-RAM and BD-RE.

31. The apparatus according to claim 1, wherein said memory form factor is an Integrated Circuit (IC), a Printed Circuit Board (PCB) on which one or more ICs are mounted, or a box-shaped enclosure.

32. The apparatus according to claim 1, wherein said first or said second bus is a Personal Area Network (PAN) or a Wide Area Network (WAN) communication link.

33. The apparatus according to claim 1, wherein said first or said second bus is a Local Area Network (LAN) communication link.

34. The apparatus according to claim 33, wherein said first or said second bus is based on Ethernet and is substantially compliant to IEEE 802.3 standard.

35. The apparatus according to claim 34, wherein said first or said second bus is based on one out of:

100BaseT/TX, 1000BaseT/TX, 10 gigabit Ethernet substantially according to IEEE Std 802.3ae-2002as standard, 40 Gigabit Ethernet, and 100 Gigabit Ethernet substantially according to IEEE P802.3ba standard.

36. The apparatus according to claim 1, further comprising encryptor/decryptor using an encryption scheme coupled between said first and second interfaces, for encrypting and decrypting digital data between said first and second buses.

37. The apparatus according to claim 36, wherein said encryption scheme is based on Advanced Encryption Standard (AES) 128, 192 or 256 bits.

38. The apparatus according to claim 1, wherein said first or said second bus is based on a multi-drop or a daisy-chain topology.

39. The apparatus according to claim 38, wherein said first or said second bus employs master/slave scheme or is based on half-duplex or full-duplex communication.

40. The apparatus according to claim 1, wherein said first or said second bus is a wired-based, point-to-point, and bit-serial bus, and wherein a timing, clocking or strobing signal is carried over dedicated wires.

41. The apparatus according to claim 1, wherein said first or said second bus is a wired-based, point-to-point, and bit-serial bus, and wherein a timing, clocking or strobing signal is carried using a self-clocking scheme.

42. The apparatus according to claim 1, wherein said first or said second bus medium is based on a fiber-optics cable, and wherein said apparatus respectively further comprising a fiber-optics connector for connecting to said fiber-optics cable.

43. The apparatus according to claim 1, wherein said power signal is Direct Current (DC) type and is carried over dedicated wires.

44. The apparatus according to claim 1, wherein said power signal is Direct Current (DC) type and is carried over the same wires carrying digital data, and wherein said apparatus further comprising a power/data splitter arrangement having first, second and third ports, wherein only digital data signal is passed between said first and second ports, and only power signal is passed between said first and third ports, and wherein said first port is coupled to said bus connector.

45. The apparatus according to claim 44, wherein said power and digital data signals are carried using Frequency Division Multiplexing (FDM), where the digital data signal is carried over a frequency band above and distinct from the power signal.

46. The apparatus according to claim 45, wherein said power/data splitter comprising a High Pass Filter (HPF) between said first and second ports and a Low Pass Filter (LPF) between said first and third ports.

47. The apparatus according to claim 44, wherein said power/data splitter comprising a transformer and a capacitor connected to the transformer windings, or wherein said power and digital data signals are carried using phantom scheme.

48. The apparatus according to claim 44, wherein said power/data splitter comprising at least two transformer having a center-tap connection.

49. The apparatus according to claim 44, wherein said power and digital data signals are carried substantially according to IEEE 802.3af-2003 or IEEE 802.3at-2009 standards.

50. The apparatus according to claim 1, wherein said first interface or said second interface comprising a transmitter and a receiver coupled to said respective connector for respectively transmitting to, and receiving from, said respective multiple wires.

51. The apparatus according to claim 50, wherein said transmitter uses differential signaling, emphasis shaping, and self-clocking line-code.

52. The apparatus according to claim 51, wherein said transmitter further employs error detection, alignment, clock-correction or channel-bonding.

53. The apparatus according to claim 50, wherein said receiver uses equalization, impedance matching termination, and Phase Locked Loop (PLL).

54. A set of the apparatus according to claim 1 and a memory, wherein said apparatus is formed as a plug-in and removable unit with said memory.

55. A set of the apparatus according to claim 1 and a computer including said processor, wherein said apparatus is formed as a plug-in and removable unit with said computer.