Spin loop delay instruction
First Claim
Patent Images
1. A computer program product for facilitating processing within a computing environment, said computer program product comprising:
- a computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising;
decoding, in a decode unit of an instruction pipeline, an instruction defined to be delayed, the instruction having a field associated therewith that indicates one or more conditions to be checked;
delaying dispatching of the instruction on a thread of the computing environment, wherein the delaying stalls dispatching of the instruction in the decode unit and stalls one or more subsequent instructions of the thread; and
dispatching the instruction based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked.
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Abstract
A Spin Loop Delay instruction. The instruction has a field associated therewith that indicates one or more conditions to be checked. Dispatching of the instruction is initially delayed. The instruction is subsequently dispatched based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked.
22 Citations
20 Claims
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1. A computer program product for facilitating processing within a computing environment, said computer program product comprising:
a computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising; decoding, in a decode unit of an instruction pipeline, an instruction defined to be delayed, the instruction having a field associated therewith that indicates one or more conditions to be checked; delaying dispatching of the instruction on a thread of the computing environment, wherein the delaying stalls dispatching of the instruction in the decode unit and stalls one or more subsequent instructions of the thread; and dispatching the instruction based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A computer system for facilitating processing within a computing environment, said computer system comprising:
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a memory; and a processor in communication with the memory, wherein the computer system is configured to perform operations, said operations comprising; decoding, in a decode unit of an instruction pipeline, an instruction defined to be delayed, the instruction having a field associated therewith that indicates one or more conditions to be checked; delaying dispatching of the instruction on a thread of the computing environment, wherein the delaying stalls dispatching of the instruction in the decode unit and stalls one or more subsequent instructions of the thread; and dispatching the instruction based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked. - View Dependent Claims (13, 14, 15, 16)
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17. A computer-implemented method of facilitating processing within a computing environment, said computer-implemented method comprising:
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decoding, in a decode unit of an instruction pipeline, an instruction defined to be delayed, the instruction having a field associated therewith that indicates one or more conditions to be checked; delaying dispatching of the instruction on a thread of the computing environment, wherein the delaying stalls dispatching of the instruction in the decode unit and stalls one or more subsequent instructions of the thread; and dispatching the instruction based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked. - View Dependent Claims (18, 19, 20)
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Specification