Over-voltage write operation of tunnel magnet-resistance (“TMR”) memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques

• US 10,656,994 B2
• Filed: 12/27/2017
• Issued: 05/19/2020
• Est. Priority Date: 10/24/2017
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Berger, Neal, Louie, Benjamin, El-Baraji, Mourad, Crudele, Lester
• Primary Examiner(s): Lamarre, Guy J
• Assistant Examiner(s): Alshack, Osman M
• Application Number:
  US15/855,910
• Publication Number:
  US 20190121694A1
• Time in Patent Office: 874 Days
• Field of Search: 714763, 714764, 714765, 714766
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A method for correcting bit defects in an STT-MRAM memory is disclosed. The method includes reading a codeword in the STT-MRAM memory, wherein the STT-MRAM memory includes a plurality of codewords, wherein each codeword includes a plurality of redundant bits. Further, the method includes mapping defective bits in the codeword to redundant bits of the plurality of redundant bits based on a mapping scheme, wherein the mapping scheme is operable to determine a manner in which the defective bits in the codeword are to be mapped to the redundant bits. Finally, the method includes replacing the defective bits in the codeword with corresponding mapped redundant bits.

Claims

1. A method for correcting bit defects in an STT-MRAM memory, the method comprising:

reading a codeword in the STT-MRAM memory, wherein the STT-MRAM memory comprises a plurality of codewords, wherein each codeword comprises a plurality of bits and a plurality of redundant bits;

mapping defective bits in the plurality of bits of the codeword to redundant bits of the plurality of redundant bits based on a mapping scheme, wherein the mapping scheme is operable to determine a manner in which the defective bits in the codeword are to be mapped to the redundant bits, wherein the mapping comprises;

determining if each bit from the defective bits represents an open circuit or a short circuit in the STT-MRAM memory;

determining a respective position of each defective bit in the codeword; and

mapping a respective redundant bit of the plurality of redundant bits to each

defective bit in accordance with a position of each defective bit;

based on the mapping, using mapped redundant bits in lieu of the defective bits in the codeword; and

performing an ECC correction operation on the codeword read from the STT-MRAM memory to correct any additional errors in the codeword.

2. The method of claim 1, wherein the reading the codeword and the mapping of the defective bits are performed substantially simultaneously.

3. The method of claim 1, wherein the mapping scheme comprises a left to right mapping scheme, wherein a left most defective bit in the codeword is mapped to a left most redundant bit of the plurality of redundant bits of the codeword, and wherein each subsequent defective bit traversing from left to right is mapped to a next available redundant bit traversing from left to right.

4. The method of claim 1, wherein the mapping scheme comprises a right to left mapping scheme, wherein a right most defective bit in the codeword is mapped to a right most redundant bit of the plurality of redundant bits of the codeword, and wherein each subsequent defective bit traversing from right to left is mapped to a next available redundant bit traversing from a right to left.

5. The method of claim 1, wherein the mapping scheme alternates between a left to right mapping scheme and a right to left mapping scheme.

6. The method of claim 1, where the mapping scheme comprises:

dividing the codeword into a plurality of segments; and

allocating one or more redundant bits from said plurality of redundant bits to each of the plurality of segments, wherein a defective bit in each segment is mapped to a redundant bit that is allocated thereto.

7. The method of claim 1 further comprising:

shorting ambiguous bits in the STT-MRAM memory, wherein the ambiguous bits have ambiguous resistances between being high or low bits; and

using the mapping scheme to map the ambiguous bits to redundant bits.

8. A method for correcting bit defects in an STT-MRAM memory, the method comprising:

reading a codeword in the STT-MRAM memory, wherein the STT-MRAM memory comprises a plurality of codewords, wherein each codeword comprises a respective plurality of bits and a respective plurality of redundant bits;

mapping each defective bit in the codeword to a respective redundant bit of the plurality of redundant bits in accordance with a mapping scheme, wherein the mapping scheme is operable to determine a manner in which the defective bits of the codeword are to be mapped to redundant bits of the codeword, wherein the mapping comprises;

determining if each defective bit represents an open circuit or a short circuit in the STT-MRAM memory;

determining a position of the defective bit in the codeword; and

mapping a redundant bit to the defective bit based on the position;

replacing the defective bits of the codeword with redundant bits of the plurality of redundant bits, wherein the defective bits are replaced with the redundant bits based on relative positions of the defective bits in accordance with the mapping scheme; and

performing an ECC correction operation on the codeword read from the STT-MRAM memory to correct any additional errors in the codeword.

9. The method of claim 8, wherein the reading the codeword and the mapping of the defective bits are performed substantially simultaneously.

10. The method of claim 8, wherein the mapping scheme comprises a left to right mapping scheme, wherein a left most defective bit in the codeword is mapped to a left most redundant bit of the plurality of redundant bits, and wherein each subsequent defective bit traversing from left to right is mapped to a next available redundant bit traversing left to right.

11. The method of claim 8, wherein the mapping scheme comprises a right to left mapping scheme, wherein a right most defective bit in the codeword is mapped to a right most redundant bit of the plurality of redundant bits, and wherein each subsequent defective bit traversing from right to left is mapped to a next available redundant bit traversing right to left.

12. The method of claim 8, wherein the mapping scheme alternates between a left to right mapping scheme and a right to left mapping scheme.

13. The method of claim 8, where the mapping scheme comprises:

dividing the codeword into a plurality of segments; and

allocating one or more redundant bits from said plurality of redundant bits to each of the plurality of segments, wherein a defective bit in each segment is mapped to a redundant bit that is allocated thereto.

14. An apparatus for correcting bit defects in an STT-MRAM memory, the apparatus comprising:

a processor;

an STT-MRAM memory comprising a plurality of codewords, wherein each codeword comprises a respective plurality of bits and a respective plurality of redundant bits, and wherein the processor is configured to;

read a codeword in the STT-MRAM memory;

map defective bits in the codeword to redundant bits of the plurality of redundant bits based on a mapping scheme, wherein the mapping scheme is operable to determine a manner in which the defective bits in the codeword are to be mapped to the redundant bits, wherein to map the defective bits, the processor is further configured to;

determine if each defective bit represents an open circuit or a short circuit in the STT-MRAM memory;

determine a position of the defective bit in the codeword; and

map a redundant bit to the defective bit based on the position;

replace the defective bits in the codeword with corresponding redundant bits as mapped and

perform an ECC correction operation on the codeword read from the STT-MRAM memory to correct any additional errors in the codeword.

15. The apparatus of claim 14, wherein the processor is configured to read the codeword and map the defective bits simultaneously.

16. The apparatus of claim 14, wherein the mapping scheme comprises a left to right mapping scheme, wherein a left most defective bit in the codeword is mapped to a left most redundant bit of the plurality of redundant bits, and wherein each subsequent defective bit traversing from a left to right is mapped to a next available redundant bit traversing left to right.

17. The apparatus of claim 14, wherein the mapping scheme comprises a right to left mapping scheme, wherein a right most defective bit in the codeword is mapped to a right most redundant bit of the plurality of redundant bits, and wherein each subsequent defective bit traversing from right to left is mapped to a next available redundant bit traversing right to left.

18. The apparatus of claim 14, wherein the mapping scheme alternates between a left to right mapping scheme and a right to left mapping scheme.

19. The apparatus of claim 14, wherein in order to implement the mapping scheme, the processor is configured to:

divide the codeword into a plurality of segments; and

allocate one or more redundant bits from said plurality of redundant bits to each of the plurality of segments, wherein a defective bit in each segment is mapped to a redundant bit that is allocated thereto.