Techniques for an all persistent memory file system

• US 10,657,068 B2
• Filed: 03/22/2018
• Issued: 05/19/2020
• Est. Priority Date: 03/22/2018
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Puthiyedath, Leena K.
• Primary Examiner(s): Doan, Khoa D
• Application Number:
  US15/928,699
• Publication Number:
  US 20190050344A1
• Time in Patent Office: 789 Days
• CPC Class Codes: G06F 12/0653 with centralised address assignment
• CPC Class Codes: G06F 12/109 for multiple virtual address spaces, e.g. segmentation G06F12/1036 takes precedence
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/657 Virtual address space management

Abstract

Examples may include techniques for an all persistent memory file system. The techniques to include allocating physical memory pages of memory devices of a persistent memory platform coupled with a computing platform. The techniques to also include storing context or relocated files to persistent memory physical address spaces for the memory devices and mapping process virtual address spaces for a working set associated with one or more instantiations of a program by circuitry at the computing platform.

Claims

1. An apparatus comprising:

circuitry used in connection with a computing platform coupled with a persistent memory platform, the circuitry to execute logic that responsive to one or more instantiations of a program by circuitry at the computing platform includes the logic to;

allocate a first portion of persistent memory physical pages of one or more memory devices of the persistent memory platform for a first processing working set of a first instantiation of the program, the allocated first portion of the persistent memory physical pages obtained from a persistent memory physical address space for the one or more memory devices;

store context specific data for the first processing working set in a first context file in the allocated first portion of the persistent memory physical pages, the first context file to include a first file offset to at least one persistent memory physical address space of the persistent physical memory address space, the first context file stored in a file format that is directly executable by a first circuitry at the computing platform; and

map a first portion of a first process virtual address space for the first processing working set to the at least one persistent memory address space via use of the first file offset as a reference to the first context file.

2. The apparatus of claim 1, comprising the context specific data for the first processing working set to include read write data pages, stack pages or heap pages associated with the first instantiation of the program by the first circuitry at the computing platform, the first circuitry including a first central processing unit.

3. The apparatus of claim 1 further comprising the logic to:

allocate a second portion of the persistent physical memory pages of the one or more memory devices of the persistent memory platform for the first processing working set of the first instantiation of the program, the allocated second portion of the persistent memory physical pages obtained from the persistent memory physical address space;

store non-context specific data for the first processing working set in one or more relocatable files in the allocated second portion of the persistent memory physical pages, the one or more relocatable file to separately include file offsets to respective persistent memory physical address spaces of the persistent physical memory address space, the one or more relocatable files stored in a file format that is directly executable by the first circuitry at the computing platform; and

map a second portion of the first process virtual address space for the first processing working set to the respective persistent memory address spaces via use of at least one of the file offsets as a reference to the one or more relocatable files.

4. The apparatus of claim 3, comprising the non-context specific data for the first processing working set to include position independent program code for the program, position independent dynamic link library code for the program or read only data for the program.

5. The apparatus of claim 3, further comprising the logic to:

allocate a third portion of persistent memory physical pages of one or more memory devices of the persistent memory platform for a second processing working set of a second instantiation of the program, the allocated third portion of the persistent memory physical pages obtained from the persistent memory physical address space;

store context specific data for the second processing working set in a second context file in the allocated third portion of the persistent memory physical pages, the second context file to include a second file offset to at least one persistent memory physical address space of the persistent physical memory address space, the second context file stored in a file format that is directly executable by a second circuitry at the computing platform; and

map a first portion of a second process virtual address space for the second processing working set to the at least one persistent memory address space via use of the second file offset as a reference to the second context file.

6. The apparatus of claim 5, comprising the context specific data for the second processing working set to include read write data pages, stack pages or heap pages associated with the second instantiation of the program by the second circuitry at the computing platform, the second circuitry to include a second central processing unit.

7. The apparatus of claim 5, comprising the one or more relocatable files capable of being shared between the first processing working set and the second processing working set.

8. The apparatus of claim 5, comprising the circuitry to execute the logic includes the first circuitry at the computing platform or the second circuitry at the computing platform.

9. The apparatus of claim 1, further comprising the computing platform.

10. The apparatus of claim 1, further comprising the persistent memory platform.

11. The apparatus of claim 10, the persistent memory platform further comprising at least one dual in-line memory module (DIMM), the one or more memory devices of the persistent memory platform maintained on the at least one DIMM.

12. The apparatus of claim 10, comprising the one or more memory devices of the persistent memory platform including volatile or non-volatile memory, wherein the volatile memory includes random-access memory (RAM), Dynamic RAM (DRAM), double data rate synchronous dynamic RAM (DDR SDRAM), static random-access memory (SRAM), thyristor RAM (T-RAM) or zero-capacitor RAM (Z-RAM) and wherein the non-volatile memory includes phase change memory that uses chalcogenide phase change material, flash memory, single or multi-level phase change memory (PCM), nanowire memory, ferroelectric transistor random access memory (FeTRAM), anti-ferroelectric memory, resistive memory including a metal oxide base, an oxygen vacancy base and a conductive bridge random access memory (CB-RAM), a spintronic magnetic junction memory, a magnetic tunneling junction (MTJ) memory, a domain wall (DW) and spin orbit transfer (SOT) memory, a thyristor based memory, a magnetoresistive random access memory (MRAM) that incorporates memristor technology, spin transfer torque MRAM (STT-MRAM).

13. A method implemented responsive to one or more instantiations of a program by circuitry used in connection with a computing platform coupled with a persistent memory platform, the method comprising:

allocating a first portion of persistent memory physical pages of one or more memory devices of the persistent memory platform for a first processing working set of a first instantiation of the program in the allocated first portion of the persistent memory physical pages, the allocated first portion of the persistent memory physical pages obtained from a persistent memory physical address space for the one or more memory devices;

storing context specific data for the first processing working set in a first context file, the first context file including a first file offset to at least one persistent memory physical address space of the persistent physical memory address space, the first context file stored in a file format that is directly executable by a first circuitry at the computing platform; and

mapping a first portion of a first process virtual address space for the first processing working set to the at least one persistent memory address space using the first file offset as a reference to the first context file.

14. The method of claim 13, comprising the context specific data for the first processing working set including read write data pages, stack pages or heap pages associated with the first instantiation of the program by the first circuitry at the computing platform, the first circuitry including a first central processing unit.

15. The method of claim 14, further comprising:

allocating a second portion of the persistent physical memory pages of the one or more memory devices of the persistent memory platform for the first processing working set of the first instantiation of the program, the allocated second portion of the persistent memory physical pages obtained from the persistent memory physical address space;

storing non-context specific data for the first processing working set in one or more relocatable files in the allocated second portion of the persistent memory physical pages, the one or more relocatable file separately including file offsets to respective persistent memory physical address spaces of the persistent physical memory address space, the one or more relocatable files stored in a file format that is directly executable by the first circuitry at the computing platform; and

mapping a second portion of the first process virtual address space for the first processing working set to the respective persistent memory address spaces using at least one of the file offsets as a reference to the one or more relocatable files.

16. The method of claim 15, comprising the non-context specific data for the first processing working set including position independent program code for the program, position independent dynamic link library code for the program or read only data for the program.

17. The method of claim 15, further comprising:

allocating a third portion of persistent memory physical pages of one or more memory devices of the persistent memory platform for a second processing working set of a second instantiation of the program, the allocated third portion of the persistent memory physical pages obtained from the persistent memory physical address space;

storing context specific data for the second processing working set in a second context file in the allocated third portion of the persistent memory physical pages, the second context file including a second file offset to at least one persistent memory physical address space of the persistent physical memory address space, the second context file stored in a file format that is directly executable by a first circuitry at the computing platform; and

mapping a first portion of a second process virtual address space for the second processing working set to the at least one persistent memory address space using the second file offset as a reference to the second context file.

18. The method of claim 17, comprising the context specific data for the second processing working set including read write data pages, stack pages or heap pages associated with the second instantiation of the program by a second circuitry at the computing platform, the second circuitry including a second central processing unit.

19. The method of claim 17, comprising the one or more relocatable files capable of being shared between the first processing working set and the second processing working set.

20. The method of claim 13, comprising the persistent memory platform capable of storing the first context file such that the first context file continues to be accessible following a power loss to the persistent memory platform and the computing platform.

21. At least one machine readable medium comprising a plurality of instructions that in response to being executed by a system used in connection with a computing platform coupled with a persistent memory platform cause the system to:

allocate, responsive to one or more instantiations of a program by circuitry at the computing platform, a first portion of persistent memory physical pages of one or more memory devices of the persistent memory platform for a first processing working set of a first instantiation of the program, the allocated first portion of the persistent memory physical pages obtained from a persistent memory physical address space for the one or more memory devices;

store context specific data for the first processing working set in a first context file in the allocated first portion of the persistent memory physical pages, the first context file to include a first file offset to at least one persistent memory physical address space of the persistent physical memory address space, the first context file stored in a file format that is directly executable by a first circuitry at the computing platform; and

map a first portion of a first process virtual address space for the first processing working set to the at least one persistent memory address space via use of the first file offset as a reference to the first context file.

22. The at least one machine readable medium of claim 21, comprising the context specific data for the first processing working set to include read write data pages, stack pages or heap pages associated with the first instantiation of the program by the first circuitry at the computing platform, the first circuitry including a first central processing unit.

23. The at least one machine readable medium of claim 21, comprising the instructions to further cause the system to:

allocate a second portion of the persistent physical memory pages of the one or more memory devices of the persistent memory platform for the first processing working set of the first instantiation of the program, the allocated second portion of the persistent memory physical pages obtained from the persistent memory physical address space;

store non-context specific data for the first processing working set in one or more relocatable files in the allocated second portion of the persistent memory physical pages, the one or more relocatable file to separately include file offsets to respective persistent memory physical address spaces of the persistent physical memory address space, the one or more relocatable files stored in a file format that is directly executable by the first circuitry at the computing platform; and

map a second portion of the first process virtual address space for the first processing working set to the respective persistent memory address spaces via use of at least one of the file offsets as a reference to the one or more relocatable files.

24. The at least one machine readable medium of claim 23, comprising the instructions to further cause the system to:

allocate a third portion of persistent memory physical pages of one or more memory devices of the persistent memory platform for a second processing working set of a second instantiation of the program, the allocated third portion of the persistent memory physical pages obtained from the persistent memory physical address space;

store context specific data for the second processing working set in a second context file in the allocated third portion of the persistent memory physical pages, the second context file to include a second file offset to at least one persistent memory physical address space of the persistent physical memory address space, the second context file stored in a file format that is directly executable by a second circuitry at the computing platform; and

map a first portion of a second process virtual address space for the second processing working set to the at least one persistent memory address space via use of the second file offset as a reference to the second context file.

25. The at least one machine readable medium of claim 24, comprising the context specific data for the second processing working set to include read write data pages, stack pages or heap pages associated with the second instantiation of the program by the second circuitry at the computing platform, the second circuitry to include a second central processing unit.

26. The at least one machine readable medium of claim 24, comprising the one or more relocatable files capable of being shared between the first processing working set and the second processing working set.