Memory device with memory cell blocks, bit line sense amplifier blocks, and control circuit connected to bit line sense amplifier blocks to control constant levels of currents supplied to sensing driving voltage lines

• US 10,658,014 B2
• Filed: 03/30/2018
• Issued: 05/19/2020
• Est. Priority Date: 09/27/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Min-su, Kim, Jong-cheol
• Primary Examiner(s): Siddique, Mushfique
• Application Number:
  US15/941,877
• Publication Number:
  US 20190096446A1
• Time in Patent Office: 781 Days
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A memory device includes memory cell blocks, bit line sense amplifier blocks, and a control circuit connected to one or more of the bit line sense amplifier blocks arranged between the memory cell blocks. The control circuit controls levels of currents respectively supplied to a first sensing driving voltage line and a second sensing driving voltage line driving bit line sense-amplifiers, to be constant. A first sensing driving control signal and/or a second sensing driving control signal, output from the sensing-matching control circuit is provided to the bit line sense amplifiers in all of the bit line sense amplifier blocks, so that the bit line sense amplifiers are constantly driven based on the constant levels of currents supplied to the first sensing driving voltage line and the second sensing driving voltage line.

Claims

1. A memory device comprising:

a plurality of memory cell blocks, where each memory cell block comprises a plurality of memory cells;

a plurality of bit line sense amplifier blocks arranged between the memory cell blocks and comprising bit line sense amplifiers performing sensing operations for sensing and amplifying data of the memory cells; and

a sensing-matching control circuit connected to one or more of the bit line sense amplifier blocks and determining levels of currents respectively supplied to a first sensing driving voltage line and a second sensing driving voltage line, wherein the first sensing driving voltage line and the second sensing driving voltage line are connected to the bit line sense amplifiers of the one or more bit line sense amplifier blocks, to which the sensing-matching control circuit is connected,

wherein the bit line sense amplifiers of the one or more bit line sense amplifier blocks are driven based on the levels of currents of the first and second sensing driving voltage lines, the levels of currents being determined by the sensing-matching control circuit,

wherein the sensing-matching control circuit applies a first internal voltage to a given sensing driving voltage line among the sensing driving voltage lines during one of the sensing operations, and

wherein the sensing-matching control circuit comprises;

a first current source;

a first sensing driving voltage driver; and

a first comparator comparing a first internal voltage of a first node connected between the first current source and an input terminal of the first sensing driving voltage driver with a first reference voltage to output a first sensing driving control signal,

wherein the first sensing driving voltage driver provides the first internal voltage to the given sensing driving voltage line based on the first sensing driving control signal.

2. The memory device of claim 1, wherein the sensing-matching control circuit comprises a voltage distributor comprising resistors connected in series and fuses connected in parallel to the resistors, wherein

the voltage distributor stores the first sensing driving control signal based on whether or not the fuses are cut, and

the levels of currents respectively supplied to the first and second sensing driving voltage lines are determined in response to the first sensing driving control signal.

3. The memory device of claim 2, wherein the sensing-matching control circuit stores the first sensing driving control signal in the voltage distributor, before the sensing operations of the bit line sense amplifiers.

4. The memory device of claim 3, wherein the first sensing driving control signal is stored in the voltage distributor in a process of manufacturing the memory device.

5. The memory device of claim 1, wherein the first sensing driving voltage driver comprises an NMOS transistor comprising a gate terminal receiving the first sensing driving control signal, and connected between the first node and the given sensing driving voltage line.

6. The memory device of claim 1, wherein the first sensing driving voltage driver comprises a PMOS transistor comprising a gate terminal receiving first sensing driving control signal, and connected between the first node and the given sensing driving voltage line.

7. The memory device of claim 1, wherein the sensing-matching control circuit comprises:

a second current source;

a second sensing driving voltage driver; and

a second comparator comparing a second internal voltage of a second node connected between the second current source and the second sensing driving voltage driver with a second reference voltage to generate a second sensing driving control signal,

wherein the second sensing driving voltage driver provides the second internal voltage to the other sensing driving voltage line based on the second sensing driving control signal.

8. The memory device of claim 7, wherein the first sensing driving voltage driver comprises a first NMOS transistor comprising a gate receiving the first sensing driving control signal, and connected between the first node and the given sensing driving voltage line, and

the second sensing driving voltage driver comprises a second NMOS transistor comprising a gate receiving the second sensing driving control signal, and connected between the second node and the other sensing driving voltage line.

9. The memory device of claim 7, wherein the first sensing driving voltage driver comprises a first PMOS transistor comprising a gate receiving the first sensing driving control signal, and connected between the first node and the given sensing driving voltage line, and

the second sensing driving voltage driver comprises a second PMOS transistor comprising a gate receiving the second sensing driving control signal, and connected between the second node and the other sensing driving voltage line.

10. The memory device of claim 1, wherein each of the bit line sense amplifiers comprises:

P-type sense amplifier sensing and amplifying a voltage difference between a bit line and a complementary bit line, to which the memory cells are connected, and supplying a high level of the amplified voltage difference, in the sensing operations;

an N-type sense amplifier sensing and amplifying the voltage difference between the bit line and the complementary bit line, to which the memory cells are connected, and supplying a low level of the amplified voltage difference, in the sensing operations; and

a precharge and equivalent circuit equalizing the bit line and the complementary bit line to a level of a precharge voltage, before the sensing operations.

11. The memory device of claim 1, wherein the sensing-matching control circuit decreases the first internal voltage when the first internal voltage is higher than the first reference voltage and increases the first internal voltage when the first internal voltage is lower than the first reference voltage.

12. A memory device comprising:

a plurality of memory cell blocks, where each memory cell block comprises a plurality of memory cells;

a plurality of bit line sense amplifier blocks arranged between the memory cell blocks and comprising bit line sense amplifiers performing operations of removing an offset voltage between a bit line and a complementary bit line, to which the memory cells are connected, and sensing and amplifying a voltage difference between the bit line and the complementary bit line; and

a sensing-matching control circuit connected to one or more of the bit line sense amplifier blocks and determining levels of currents respectively supplied to a first sensing driving voltage line and a second sensing driving voltage line, wherein the first sensing driving voltage line and the second sensing driving voltage line are connected to the bit line sense amplifiers of the one or more bit line sense amplifier blocks, to which the sensing-matching control circuit is connected,

wherein the bit line sense amplifiers of the one or more bit line sense amplifier blocks are driven based on the levels of currents of the first and second sensing driving voltage lines, the levels of currents being determined by the sensing-matching control circuit,

wherein the sensing-matching control circuit comprises a current source, a comparator, and a transistor connected between the current source and one of the sensing driving voltage lines,

wherein the comparator receives a voltage of a node connected between the current source and an input terminal of the transistor and a reference voltage, and provides an output to a gate terminal of the transistor.

13. The memory device of claim 12, wherein the sensing-matching control circuit comprises a voltage distributor comprising resistors connected in series and fuses connected in parallel to the resistors, wherein

the voltage distributor stores a sensing driving control signal based on whether or not the fuses are cut, and

the levels of currents respectively supplied to the first and second sensing driving voltage lines are determined in response to the sensing driving control signal.

14. The memory device of claim 13, wherein the sensing-matching control circuit stores the sensing driving control signal in the voltage distributor, before the operations of removing the offset voltage via the bit line sense amplifiers.

15. The memory device of claim 12, wherein the sensing-matching control circuit compares a level of a voltage of a first internal voltage line with a level of a first reference voltage, generates a sensing driving control signal when the level of the voltage of the first internal voltage line is equal to the level of the first reference voltage, and drives the first sensing driving voltage line based on the determined level of current of the first sensing driving voltage line, in response to the sensing driving control signal.

16. The memory device of claim 12, wherein the sensing-matching control circuit compares a level of a voltage of a first internal voltage line with a level of a first reference voltage, generates a sensing driving control signal when the level of the voltage of the second internal voltage line is equal to the level of the first reference voltage, and drives the second sensing driving voltage line based on the determined level of current of the second sensing driving voltage line, in response to the sensing driving control signal.

17. The memory device of claim 12, wherein each of the bit line sense amplifiers comprises:

a first isolation transistor connecting the bit line with a sensing bit line in response to an isolation signal;

a first offset removal transistor connecting the bit line with a complementary sensing bit line in response to an offset removal signal;

a P-type sense amplifier supplying a high level of the amplified voltage difference in sensing operations;

an N-type sense amplifier supplying a low level of the amplified voltage difference in the sensing operations;

a second isolation transistor connecting the complementary bit line with the complementary sensing bit line in response to the isolation signal; and

a second offset removal transistor connecting the complementary bit line with the sensing bit line in response to the offset removal signal.