Word line pulse width control circuit in static random access memory

• US 10,658,026 B2
• Filed: 05/03/2018
• Issued: 05/19/2020
• Est. Priority Date: 05/26/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Singh, Anjana, Lee, Cheng Hung, Shieh, Hau-Tai, Chen, Yi-Tzu
• Primary Examiner(s): Tran, Michael T
• Application Number:
  US15/969,834
• Publication Number:
  US 20180342288A1
• Time in Patent Office: 747 Days
• Field of Search: 365154, 365205
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

Devices and methods are provided for word line pulse width control for a static random access memory (SRAM) devices. An inverter within a pre-decoder circuit receives a first input of a clocked address. The inverter determines an output based on the clocked address. An electrical load of a decoder driver circuit of the SRAM device is modified based on the output. Current to a transistor coupled at a common node is provided. The transistor is configured to electrically couple a plurality of transistors of the decoder driver circuit within the SRAM device.

Claims

1. A control circuit for minimizing a static noise margin of a static random access memory device comprising:

a first transistor comprising a gate and a source/drain terminal;

an inverter comprising an input node coupled to the gate of the first transistor and an output node; and

a second transistor comprising a gate, a first source/drain terminal, and a second source/drain terminal, the gate of the second transistor being coupled to the output node of the inverter and the first source/drain terminal of the second transistor being coupled in series to the source/drain terminal of the first transistor, and wherein the second source/drain terminal is coupled to a decoder driver circuit,

wherein the second transistor is configured to charge a load of a common decoder line so as to reduce an effective load of the decoder driver circuit.

2. The control circuit of claim 1, wherein the first transistor and the second transistor are coupled together at a common node, the common node coupled to one or more driver circuits.

3. The control circuit of claim 1, wherein the first transistor is coupled to a common decoder line of a static random access memory (SRAM) device.

4. The control circuit of claim 1, wherein the inverter is driven by a first voltage and the second transistor is driven by a second voltage.

5. The control circuit of claim 4, wherein the first and second voltages are voltages independent of one another.

6. The control circuit of claim 4, wherein another source/drain terminal of the second transistor is coupled to the second voltage.

7. A static random access memory (SRAM) device comprising:

at least two decoder driver circuits electrically coupled together via a common decoder line;

a transistor electrically coupled to the at least two decoder driver circuits via the common decoder line; and

an inverter electrically coupled to the transistor,

wherein the transistor is configured to charge an electrical load of the at least two decoder driver circuits so as to reduce an effective load of the at least two decoder driver circuits, and

wherein the transistor charges a load of the common decoder line so as to reduce an effective load of the at least two decoder driver circuits.

8. The SRAM device of claim 7, further comprising another transistor electrically coupled to the common decoder line between a source/drain terminal of the transistor and an input node of the inverter.

9. The SRAM device of claim 7, wherein the common decoder line is coupled to one or more transistors within each decoder driver circuit.

10. The SRAM device of claim 7, wherein the inverter is driven by a first voltage and the transistor is driven by a second voltage.

11. The SRAM device of claim 10, wherein the first and second voltages are voltages independent of one another.

12. The SRAM device of claim 10, wherein a source/drain terminal of the transistor is coupled to the second voltage.

20. The SRAM device of claim 7, wherein the inverter comprises an input node electrically coupled to a gate of the transistor.

13. A method in a static random access memory (SRAM) device comprising:

generating, at a gate of a first transistor, a first input comprising a clocked address;

receiving, by an inverter, the clocked address;

determining, by the inverter, an output based on the clocked address;

modifying an electrical load of a decoder driver circuit of the SRAM device based on the output; and

providing current to a transistor coupled at a common node configured to electrically couple a plurality of transistors within the decoder driver circuit.

14. The method of claim 13, wherein the transistor is configured to charge the electrical load of the decoder driver circuit so as to reduce an effective load of the decoder driver circuit.

15. The method of claim 13, wherein a common decoder line is coupled to one or more transistors of the decoder driver circuit.

16. The method of claim 13, wherein the inverter is driven by a first voltage and the transistor is driven by a second voltage.

17. The method of claim 16, wherein the first and second voltages are voltages independent of one another.

18. The method of claim 16, wherein a source/drain terminal of the transistor is coupled to the second voltage.

19. The method of claim 16, wherein the electrical load is reduced at the common node when the first voltage first voltage is greater than the second voltage.