Synaptic crossbar memory array

• US 10,658,030 B2
• Filed: 11/29/2017
• Issued: 05/19/2020
• Est. Priority Date: 11/29/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Afzali-Ardakani, Ali, Gershon, Talia S., Hashemi, Pouya, Hekmatshoartabari, Bahman
• Primary Examiner(s): Huang, Min
• Application Number:
  US15/826,654
• Publication Number:
  US 20190164597A1
• Time in Patent Office: 902 Days
• Field of Search: 365148
• CPC Class Codes: G11C 11/54 using elements simulating biological cells, e.g. neuron
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/52 Structure characterized by the electrode material, shape, etc.
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/021 Formation of the switching material, e.g. layer deposition
• CPC Class Codes: H10N 70/061 Patterning of the switching material
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/884 Other compounds of groups 13-15, e.g. elemental or compound semiconductors

Abstract

A method of forming an Integrated Circuit (IC) chip, the IC chip and an on-chip synaptic crossbar memory array. Chip devices are formed on a surface of a semiconductor wafer. A connective layer is formed above the chip devices. A bottom electrode layer is formed on the connective layer. A neuromorphic synapse layer is formed above the bottom electrode layer with each synapse on a bottom electrode. Upper electrodes are formed above the synapses and orthogonal to bottom electrode lines. Each synapse being beneath an upper electrode where the upper electrode crosses a bottom electrode. Upper electrodes are refractory metal and the bottom electrodes are copper, or vice versa.

Claims

1. A method of forming an Integrated Circuit (IC) chip, said method comprising:

forming a plurality of transistors on a surface of a semiconductor wafer;

forming a connective layer above said plurality of transistors;

forming a bottom electrode layer on said connective layer, said bottom electrode layer including one or more bottom electrode lines of a first metal and connected to ones said plurality of transistors through said connective layer;

forming a one or more amorphous semiconductor synapses on said one or more bottom electrode lines;

forming an upper electrode layer above said one or more amorphous semiconductor synapses, said upper electrode layer including one or more upper electrode lines of a second metal oriented orthogonally to said one or more bottom electrode lines and connected to others of said plurality of transistors, each amorphous semiconductor synapse being between a bottom electrode line and an upper electrode line, said second metal being different than the first and one of said first metal and said second metal being a refractory metal; and

completing chip fabrication.

2. A method as in claim 1, wherein said amorphous semiconductor comprises an amorphous germanium.

3. A method as in claim 1, wherein said second metal is said refractory metal forming said one or more upper electrode lines, the refractory metal lines forming Schottky barrier diodes at said one or more amorphous semiconductor synapses.

4. A method as in claim 1, wherein said upper electrode lines are copper lines forming resistive contacts on said amorphous semiconductor layer and said refractory metal is tungsten.

5. A method as in claim 1, wherein said refractory metal is selected from tungsten (W), titanium (Ti), titanium nitride (TiN) or a combinations thereof.

6. A method as in claim 5, wherein said refractory metal is tungsten, and wherein at said each amorphous semiconductor synapse one of said first metal and said second metal forms a resistive contact and the other of said first metal and said second metal forms a Schottky barrier junction.

7. A method as in claim 5, wherein said bottom electrode lines are copper lines forming resistive contacts.

8. A method as in claim 1, wherein forming said one or more amorphous semiconductor synapses comprises:

forming said amorphous semiconductor layer on said bottom electrode layer;

patterning said amorphous semiconductor layer, patterning said amorphous semiconductor layer defining said one or more amorphous semiconductor ridges, each amorphous semiconductor ridge being coextensive with one of said bottom electrode lines; and

filling with dielectric material between said one or more amorphous semiconductor synapses, a synapse being defined wherever an upper electrode line crosses a ridge.

9. A method as in claim 8, wherein said amorphous semiconductor layer comprises an amorphous germanium layer, and forming said one or more amorphous semiconductor synapses further comprises forming connective interlevel vias through said dielectric material, said one or more upper electrode lines connecting to said others through respective said connective interlevel vias.

10. An alterable synapse array comprising:

a plurality of transistors on a device layer;

a connective layer on said device layer, interlevel vias in said connective layer connecting to selected transistors;

one or more bottom electrode lines of a first metal on said connective layer, each bottom electrode line connecting to at least one interlevel via;

one or more amorphous semiconductor synapses, each synapse being on one of said one or more bottom electrode lines; and

an upper electrode layer above said one or more amorphous semiconductor synapses, said upper electrode layer including one or more upper electrode lines of a second metal oriented orthogonally to said one or more bottom electrode lines and connected to others of said plurality of transistors, each amorphous semiconductor synapse being between a respective bottom electrode line and an upper electrode line, said second metal being different than the first and one of said first metal and said second metal being a refractory metal.

11. An alterable synapse array as in claim 10, wherein said one or more bottom electrode lines are a plurality of copper lines resistively connected to said one or more amorphous semiconductor synapses.

12. An alterable synapse array as in claim 10, wherein the amorphous semiconductor synapses are amorphous germanium synapses.

13. An alterable synapse array as in claim 12, wherein

said one or more upper electrode lines are a plurality of refractory metal lines, a Schottky barrier junction being formed at the contact of one of said plurality of refractory metal lines to a respective amorphous germanium synapse;

the amorphous germanium in each said synapse has a first selected resistance; and

applying a selected voltage across a respective bottom electrode line and respective upper electrode line for a selected period of time causes Joule heating to said synapse, said Joule heating switching the amorphous germanium resistance to a second selected resistance.

14. An alterable synapse array as in claim 13, wherein said selected voltage ranges from 0.5-2V, and said selected period is one to one hundred nanoseconds (1-100 ns) long.

15. An alterable synapse array as in claim 13, wherein said refractory metal is selected from a group consisting of tungsten (W), titanium (Ti), titanium nitride (TiN) or a combinations thereof.

16. An alterable synapse array as in claim 13, wherein said refractory metal is tungsten.

17. An alterable synapse array as in claim 10, wherein said upper electrode lines are a plurality of refractory metal lines, a Schottky barrier junction being formed at the contact of one of said plurality of refractory metal lines to a respective amorphous semiconductor synapse, and said one or more bottom electrode lines are a plurality of copper lines resistively connected to said one or more amorphous semiconductor synapses.

18. An Integrated Circuit (IC) chip comprising:

a plurality of transistors on a device layer;

a connective layer on said device layer, interlevel vias in said connective layer connecting to selected transistors;

an alterable synapse array comprising;

a bottom electrode layer on said connective layer, said bottom electrode layer including one or more bottom electrode lines of a first metal oriented in a first direction, each bottom electrode line connecting to at least one interlevel via,

one or more amorphous semiconductor ridges, each being on, and coextensive with, one of said one or more bottom electrode lines,

one or more amorphous semiconductor synapses, each synapse being on one of said one or more bottom electrode lines, and

an upper electrode layer above said one or more amorphous semiconductor ridges, said upper electrode layer including one or more upper electrode lines of a second metal oriented orthogonally to said one or more bottom electrode lines and connected to others of said plurality of transistors, amorphous semiconductor synapses being formed in said ridges between bottom electrode lines and upper electrode lines; and

a plurality of wiring layers connecting said plurality of transistors into IC chip circuits.

19. An IC chip as in claim 18, wherein

said one or more bottom electrode lines comprises a plurality of bottom electrode lines;

said one or more upper electrode lines comprises a plurality of upper electrode lines;

said one or more amorphous semiconductor synapses comprises a plurality of amorphous germanium ridges and each having a resistive connection to one electrode and a Schottky barrier junction connected to the other electrode, said each amorphous semiconductor synapse having a first selected resistance; and

applying a selected voltage across a respective bottom electrode line and upper electrode line for a selected period of time causes Joule heating to the respective synapse, said Joule heating switching the amorphous germanium resistance for selected synapse to a second selected resistance.

20. An IC chip as in claim 19, wherein lines in one of said plurality of bottom electrode lines and said plurality of upper electrode lines are copper resistively connected to said amorphous semiconductor synapses and lines in the other are a refractory metal selected from a group consisting of tungsten (W), titanium (Ti), titanium nitride (TiN) or a combinations thereof.