Chip package and method of forming the same

• US 10,658,258 B1
• Filed: 02/21/2019
• Issued: 05/19/2020
• Est. Priority Date: 02/21/2019
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Pan, Kuo-Lung, Tsai, Hao-Yi, Kuo, Tin-Hao
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US16/281,094
• Time in Patent Office: 453 Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/214 Connecting portions
• CPC Class Codes: H01L 2224/24147 the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/28 Encapsulations, e.g. encapsulating layers, coatings, e.g. for protectionH01L23/552 takes precedence; insulating layers for contacts or interconnections H01L23/5329
• CPC Class Codes: H01L 23/293 : Organic, e.g. plastic
• CPC Class Codes: H01L 23/31 : characterised by the arrangement or shape
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 : Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H01L 2924/35121 : Peeling or delaminating

Abstract

A chip package including a first semiconductor die, a support structure and a second semiconductor die is provided. The first semiconductor die includes a first dielectric layer and a plurality of conductive vias, the first dielectric layer includes a first region and a second region, the conductive vias is embedded in the first region of the first dielectric layer; a plurality of conductive pillars is disposed on and electrically connected to the conductive vias. The second semiconductor die is stacked over the support structure and the second region of the first dielectric layer; and an insulating encapsulant encapsulates the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

Claims

1. A chip package, comprising:

a first semiconductor die comprising a first dielectric layer and a plurality of conductive vias, the first dielectric layer comprising a first region and a second region, the conductive vias being embedded in the first region of the first dielectric layer;

a plurality of conductive pillars disposed on and electrically connected to the conductive vias;

a support structure;

a second semiconductor die stacked over the support structure and the second region of the first dielectric layer; and

an insulating encapsulant encapsulating the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the insulating encapsulant comprises;

a first encapsulation portion laterally encapsulating the first semiconductor die and the support structure; and

a second encapsulation portion connected to the first encapsulation portion and laterally encapsulating the second semiconductor die and the conductive pillars,

wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

2. The chip package as claimed in claim 1, wherein the support structure comprises a semiconductor substrate and a second dielectric layer disposed on the semiconductor substrate.

3. The chip package as claimed in claim 1, wherein the support structure and the second semiconductor die are substantially identical in thickness.

4. The chip package as claimed in claim 1, wherein the second semiconductor die is adhered with top surfaces of the support structure and the first semiconductor die through an adhesion layer.

5. The chip package as claimed in claim 1, wherein the support structure is spaced apart from the first semiconductor die.

6. The chip package as claimed in claim 1, wherein the second region of the first dielectric layer is free of conductive vias.

7. The chip package as claimed in claim 1, wherein top surfaces of the conductive pillars and a top surface of the second semiconductor die are substantially coplanar.

8. The chip package as claimed in claim 1, wherein a contact interface is between the first encapsulation portion and the second encapsulation portion, the contact interface is substantially level with a top surface of the support structure and a top surface of the first semiconductor die.

9. The chip package as claimed in claim 1, further comprising a redistribution circuit structure disposed over the second semiconductor die, the insulating encapsulant and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the redistribution circuit structure and the conductive pillars.

10. A chip package, comprising:

an insulating encapsulant;

a first semiconductor die embedded in the insulating encapsulant, the first semiconductor die comprising a first dielectric layer and a plurality of conductive vias embedded in the first dielectric layer;

a dummy die embedded in the insulating encapsulant;

a plurality of conductive pillars disposed on the conductive vias and embedded in the insulating encapsulant;

a second semiconductor die embedded in the insulating encapsulant, the second semiconductor die being stacked over the dummy die and covering a portion of the first dielectric layer, and the conductive pillars and the second semiconductor die being spaced apart from each other by a first portion of the insulating encapsulant; and

a redistribution circuit structure disposed over the second semiconductor die, the insulating encapsulant and the conductive pillars, wherein the second semiconductor die is electrically connected to the first semiconductor die through the redistribution circuit structure and the conductive pillars.

11. The chip package as claimed in claim 10, wherein the dummy die and the first semiconductor die being spaced apart from each other by a second portion of the insulating encapsulant.

12. The chip package as claimed in claim 11, wherein the dummy die and the first semiconductor die are substantially identical in coefficient of thermal expansion (CTE).

13. The chip package as claimed in claim 11, wherein the dummy die and the second semiconductor die are substantially identical in thickness.

14. The chip package as claimed in claim 11, wherein the second semiconductor die is adhered with top surfaces of the dummy die and the first semiconductor die through an adhesion layer.

15. The chip package as claimed in claim 11, wherein the portion of the first dielectric layer covered by the second semiconductor die is free of conductive vias.

16. The chip package as claimed in claim 11, wherein the insulating encapsulant comprises a first encapsulation portion and a second encapsulation portion connected to the first encapsulation portion,

the first semiconductor die and the dummy die are embedded in the first encapsulation portion, and

the second semiconductor die and the conductive pillars are embedded in the second encapsulation portion.

17. The chip package as claimed in claim 16, wherein an interface is between the first encapsulation portion and the second encapsulation portion, the contact interface is substantially level with a top surface of the dummy die and a top surface of the first semiconductor die.

18. A method of forming a chip package, comprising:

providing a support structure and a first semiconductor die over a carrier, the first semiconductor die comprising a first dielectric layer and a plurality of conductive vias covered by the first dielectric layer, the first dielectric layer comprising a first region and a second region, the conductive vias being embedded in the first region of the first dielectric layer;

laterally encapsulating the support structure and the first semiconductor die with a first encapsulation portion;

forming conductive pillars on the conductive vias;

stacking a second semiconductor die over the support structure and the second region of the first dielectric layer; and

laterally encapsulating the second semiconductor die and the conductive pillars with a second encapsulation portion, wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

19. The method for forming a chip package as claimed in claim 18, wherein laterally encapsulating the support structure and the first semiconductor die with the first encapsulation portion comprises:

forming an insulating material on the carrier to encapsulate the support structure and the first semiconductor die; and

partially removing the insulating material and the first dielectric layer to reveal the support structure and the conductive vias of the first semiconductor die to form the first encapsulation portion.

20. The method for forming a chip package as claimed in claim 18, further comprising:

forming a redistribution circuit structure over the second semiconductor die and the conductive pillars, wherein the redistribution circuit structure electrically connects the second semiconductor die to the conductive pillars.