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Chip package and method of forming the same

  • US 10,658,258 B1
  • Filed: 02/21/2019
  • Issued: 05/19/2020
  • Est. Priority Date: 02/21/2019
  • Status: Active Grant
First Claim
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1. A chip package, comprising:

  • a first semiconductor die comprising a first dielectric layer and a plurality of conductive vias, the first dielectric layer comprising a first region and a second region, the conductive vias being embedded in the first region of the first dielectric layer;

    a plurality of conductive pillars disposed on and electrically connected to the conductive vias;

    a support structure;

    a second semiconductor die stacked over the support structure and the second region of the first dielectric layer; and

    an insulating encapsulant encapsulating the first semiconductor die, the second semiconductor die, the support structure and the conductive pillars, wherein the insulating encapsulant comprises;

    a first encapsulation portion laterally encapsulating the first semiconductor die and the support structure; and

    a second encapsulation portion connected to the first encapsulation portion and laterally encapsulating the second semiconductor die and the conductive pillars,wherein the second semiconductor die is electrically connected to the first semiconductor die through the conductive pillars.

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