Thermal extraction of single layer transfer integrated circuits

• US 10,658,386 B2
• Filed: 07/19/2018
• Issued: 05/19/2020
• Est. Priority Date: 07/19/2018
• Status: Active Grant

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Paul, Abhijeet, Dowling, Richard James, Yamada, Hiroshi, Duvallet, Alain, Reedy, Ronald Eugene
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US16/040,295
• Publication Number:
  US 20200027898A1
• Time in Patent Office: 670 Days
• Field of Search: 257347
• CPC Class Codes: H01L 21/4882 Assembly of heatsink parts
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

A FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems. In some embodiments, electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away from the FET to generally orthogonal thermal pathways, and thence to thermal pads externally accessible at the “top” of the completed IC. In some embodiments having a thermally-conductive handle wafer, electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. In some embodiments, the lateral thermal paths may use dummy gates configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways.

Claims

1. A thermal conduction structure for an integrated circuit transistor device made using a back-side access process and mounted on a handle wafer such that a gate of the transistor device is oriented towards the handle wafer, including:

(a) at least one laterally-extending thermal path fabricated in conjunction with the integrated circuit transistor device and having a near portion in close thermal contact with the transistor device, and a far portion sufficiently spaced away from the transistor device in a lateral direction from the transistor device so as to be couplable to a generally orthogonal thermal pathway, each laterally-extending thermal path being substantially electrically isolated from the transistor device; and

(b) at least one generally orthogonal thermal pathway thermally coupled to at least one laterally-extending thermal path and configured to convey heat from the at least one laterally-extending thermal path to at least one of (i) at least one externally accessible thermal pad, or (ii) the handle wafer.

2. The invention of claim 1, wherein at least one of the at least one laterally-extending thermal path is spaced from the transistor device by an electrically isolating structure.

3. The invention of claim 1, wherein at least one of the at least one laterally-extending thermal path is spaced from the transistor device by an electrically isolating structure formed by a shallow trench isolation process.

4. The invention of claim 1, wherein at least one of the at least one laterally-extending thermal path is formed at least in part by at least one metallization layer.

5. The invention of claim 1, wherein the handle wafer is spaced from the transistor device by a passivation layer, and the at least one generally orthogonal thermal pathway includes at least one thermal via formed through the passivation layer sufficiently so as to be thermally coupled to the handle wafer.

6. A method of making a thermal conduction structure for an integrated circuit transistor device made using a back-side access process and mounted on a handle wafer such that a gate of the transistor device is oriented towards the handle wafer, including:

(a) fabricating at least one laterally-extending thermal path having a near portion in close thermal contact with the transistor device, and a far portion sufficiently spaced away from the transistor device in a lateral direction from the transistor device so as to be couplable to a generally orthogonal thermal pathway, each laterally-extending thermal path being substantially electrically isolated from the transistor device; and

(b) fabricating at least one generally orthogonal thermal pathway thermally coupled to at least one laterally-extending thermal path and configured to convey heat from the at least one laterally-extending thermal path to at least one of (i) at least one externally accessible thermal pad, or (ii) the handle wafer.

7. The method of claim 6, further including spacing at least one of the at least one laterally-extending thermal path from the transistor device by an electrically isolating structure.

8. The method of claim 6, further including spacing at least one of the at least one laterally-extending thermal path from the transistor device by an electrically isolating structure formed by a shallow trench isolation process.

9. The method of claim 6, further including fabricating at least one laterally-extending thermal path at least in part out of a metallization layer.

10. The method of claim 6, further including spacing the handle wafer from the transistor device by a passivation layer, and forming at least one thermal via through the passivation layer sufficiently so as to be thermally coupled to the handle wafer and to at least one generally orthogonal thermal pathway.

11. An integrated circuit structure including:

(a) a silicon island formed on a buried insulator layer;

(b) a transistor device formed in and/or on a first surface of the silicon island, the transistor device including a source, a drain, a body, a gate insulating layer formed on the body, and a gate formed on the gate insulating layer, the gate defining a first orientation of the transistor device with respect to the silicon island;

(c) at least one electrically isolating and thermally conductive structure formed in the silicon island and configured to electrically isolate a first portion of the silicon island containing the transistor device from a corresponding edge portion of the silicon island;

(d) at least one laterally-extending thermal path having a near portion in close thermal contact with a corresponding edge portion of the silicon island, and a far portion sufficiently spaced away from the corresponding edge portion of the silicon island in a lateral direction with respect to the transistor device so as to be couplable to a generally orthogonal thermal pathway, each laterally-extending thermal path being substantially electrically isolated from the transistor device by at least a corresponding electrically isolating and thermally conductive structure; and

(e) at least one generally orthogonal thermal pathway thermally coupled to at least one laterally-extending thermal path and configured to convey heat from the at least one laterally-extending thermal path to at least one of (i) at least one externally accessible thermal pad, or (ii) a handle wafer affixed indirectly to the buried insulator layer such that the first orientation of the transistor device is directed towards the handle wafer;

wherein heat generated by the transistor device will flow laterally through the first portion of the silicon island, thence through the at least one electrically isolating and thermally conductive structure, and thence through the corresponding edge portion of the silicon island, and thereafter flow from the corresponding edge portion of the silicon island through the corresponding at least one laterally-extending thermal path to the at least one generally orthogonal thermal pathway.

12. The invention of claim 11, wherein at least one of the at least one laterally-extending thermal path is formed at least in part by at least one metallization layer.

13. The invention of claim 11, wherein at least one of the at least one laterally-extending thermal path is in direct contact with the corresponding edge portion of the silicon island.