Virtual drain for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches

• US 10,658,390 B2
• Filed: 07/10/2018
• Issued: 05/19/2020
• Est. Priority Date: 07/10/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Nowak, Edward J., Taylor, Richard F., Ethirajan, Tamilmani
• Primary Examiner(s): Le, Dung A.
• Application Number:
  US16/031,407
• Publication Number:
  US 20200020721A1
• Time in Patent Office: 679 Days
• Field of Search: None
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to virtual drains for decreased harmonic generation in fully depleted SOI (FDSOI) RF switches and methods of manufacture. The structure includes one or more active devices on a semiconductor on insulator material which is on top of a substrate; and a virtual drain region composed of a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate.

Claims

1. A structure comprising:

one or more active devices on a semiconductor on insulator material which is on top of a substrate;

a virtual drain region comprising a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate, and the virtual drain region being spaced apart from a source/drain region of an adjacent device of the one or more active devices;

a shallow trench isolation region partly within the virtual drain region, wherein an edge of the virtual drain region is remote from an edge of the shallow trench isolation region; and

a doped skin on the shallow trench isolation region, facing the adjacent device of the one or more active devices.

2. The structure of claim 1, wherein the semiconductor on insulator material is fully depleted and the one or more active deices are fully depleted silicon on insulator transistors.

3. The structure of claim 2, wherein the virtual drain region is a N-type well region below a surface of the substrate.

4. The structure of claim 3, further comprising a contact which applies a voltage bias to the N-type well region, wherein the voltage bias is at least as positive as a DC-averaged RF voltage plus a bulk threshold above ground.

5. The structure of claim 1, wherein the virtual drain region extends to underneath the source/drain region of the adjacent device of the one or more active devices.

6. The structure of claim 1, further comprising a gate structure formed directly on the shallow trench isolation region.

7. The structure of claim 6, wherein the gate structure is a metal which is biased above a bulk threshold voltage, and the virtual drain region is more positive than a threshold of the gate structure.

8. The structure of claim 1, further comprising a contact to the virtual drain region which applies a voltage to the virtual drain region.

9. A structure comprising:

a substrate;

an insulating material on the substrate;

a fully depleted semiconductor material on the insulating material;

a plurality of active devices on the fully depleted semiconductor material;

a virtual drain region within the substrate, adjacent to at least active device of the plurality of active devices, and which is spaced apart from a drain/source region of an adjacent active device of the plurality of devices; and

a contact which biases the virtual drain region to collect electrons from beneath the plurality of active devices; and

a shallow trench region partially in the virtual drain region and having an edge extending closer to the adjacent active device than the virtual drain region.

10. The structure of claim 9, wherein the virtual drain region is a N-well region.

11. The structure of claim 9, wherein the virtual drain region extends to and overlaps with a drain/source region of the adjacent active device of the plurality of devices.

12. The structure of claim 9, wherein the shallow trench isolation region includes a doped skin at a position closer to the adjacent active device than the virtual drain region.

13. The structure of claim 9, further comprising a gate structure or metal line above the shallow trench isolation region, which provides a voltage bias to the shallow trench isolation region.

14. A structure comprising:

one or more active devices on a semiconductor on insulator material which is on top of a substrate;

a virtual drain region comprising a well region within the substrate and spaced apart from an active region of the one or more devices, the virtual drain region configured to be biased to collect electrons which would accumulate in the substrate;

a shallow trench isolation region partly within the virtual drain region, wherein an edge of the virtual drain region is remote from an edge of the shallow trench isolation region; and

a metal line formed above the shallow trench isolation region on an insulator material,

wherein the metal line provides a voltage bias to the shallow trench isolation region to attract the electrons for collection in the virtual drain region, and

the virtual drain region is spaced apart from a source/drain region of an adjacent device of the one or more active devices.