Semiconductor device and method of manufacturing thereof

• US 10,658,418 B2
• Filed: 04/30/2018
• Issued: 05/19/2020
• Est. Priority Date: 09/24/2015
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: Kasai, Hiroki
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): Fox, Brandon C
• Application Number:
  US15/966,601
• Publication Number:
  US 20180247970A1
• Time in Patent Office: 750 Days
• Field of Search: 257347
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14658 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 27/14659 Direct radiation imagers structures
• CPC Class Codes: H01L 27/14665 Imagers using a photoconductor layer
• CPC Class Codes: H01L 27/14676 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H10K 39/36 Devices specially adapted for detecting X-ray radiation

Abstract

A semiconductor device includes a first semiconductor layer of a first conductivity type having a first surface on one side thereof and a second surface on an opposite side thereof, and having an element therein, a second semiconductor layer of a second conductivity type having a circuit element formed therein, the second semiconductor layer being formed at the one side of the first surface of the first semiconductor layer, an insulating layer disposed on the first surface of the first semiconductor layer, and a charge-attracting layer configured to attract electrical charges generated in the insulating layer when a predetermined voltage is supplied to the charge-attracting layer.

Claims

1. A semiconductor device, comprising:

a first semiconductor layer of a first conductivity type having a first surface on one side thereof and a second surface on an opposite side thereof, and having an element therein;

a second semiconductor layer of a second conductivity type having a circuit element formed therein, the second semiconductor layer being formed at the one side of the first surface of the first semiconductor layer;

an insulating layer disposed on the first surface of the first semiconductor layer; and

a charge-attracting layer configured to attract electrical charges generated in the insulating layer when a predetermined voltage is supplied to the charge-attracting layer.

2. The semiconductor device according to claim 1, wherein the predetermined voltage is lower than a voltage supplied to the circuit element.

3. The semiconductor device according to claim 1, wherein the predetermined voltage has a ground level.

4. The semiconductor device according to claim 1, wherein the insulating layer has a withstand voltage between the second semiconductor layer and the charge-attracting layer greater than the predetermined voltage.

5. The semiconductor device according to claim 1, wherein

the circuit element includes a field-effect transistor, and

the charge-attracting layer is embedded in the insulating layer, having two regions isolated each other, the two regions being disposed in relation to one and another of ends of the field-effect transistor in a gate width direction, respectively, and extending in a gate length direction in a plan view, so as to attract the electrical charges.

6. The semiconductor device according to claim 1, wherein

the circuit element includes a field-effect transistor, and

the charge-attracting layer is embedded in the insulating layer, surrounding the field-effect transistor in a plan view, and is disposed in relation to the field-effect transistor so as to attract the electrical charges.

7. The semiconductor device according to claim 1, further comprising a predetermined potential region of the second conductivity type that is formed in the first semiconductor layer so as to cover an area in which the charge-attracting layer is formed in a plan view, the predetermined potential region including a contact region in which the predetermined voltage is supplied.

8. The semiconductor device according to claim 1, further comprising:

an intermediate semiconductor layer formed in the insulating layer between the first semiconductor layer and the second semiconductor layer; and

a predetermined potential region of the first conductivity type that is formed in the intermediate semiconductor layer so as to cover an area in which the charge-attracting layer is formed in a plan view, the predetermined potential region including a contact region in which the predetermined voltage is supplied.