Nanosheet transistor with robust source/drain isolation from substrate

• US 10,658,459 B2
• Filed: 08/20/2019
• Issued: 05/19/2020
• Est. Priority Date: 04/30/2018
• Status: Active Grant

• Current Assignee: Rapidus Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chao, Robin Hsin Kuo, Cheng, Kangguo, Chi, Cheng, Xie, Ruilong, Zhang, John H.
• Primary Examiner(s): Amer, Mounir S
• Application Number:
  US16/545,867
• Publication Number:
  US 20200006476A1
• Time in Patent Office: 273 Days
• Field of Search: None
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A substrate structure for a nanosheet transistor includes a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers. The substrate structure includes at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate. The substrate structure includes a u-shaped portion formed at a bottom portion of the at least one trench. The u-shaped portion includes a bottom cavity. The substrate structure further includes a first liner disposed upon the u-shaped portion of the at least one trench, and a second liner disposed on the first liner. The substrate structure further includes a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.

Claims

1. An apparatus, comprising:

a substrate structure having a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers, the substrate structure including at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate;

a u-shaped portion formed at a bottom portion of the at least one trench, the u-shaped portion including a bottom cavity;

a first liner disposed upon the u-shaped portion of the at least one trench;

a second liner disposed on the first liner; and

a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.

2. The apparatus of claim 1, further comprising:

a plurality of recesses disposed between the nanosheet layers, wherein the third liner is further disposed within the plurality of recesses to form a plurality of inner spacers between the nanosheet layers.

3. The apparatus of claim 1, further comprising:

a source/drain epitaxy disposed upon the bottom inner spacer.

4. The apparatus of claim 1, further comprising:

a gate material disposed between the nanosheet layers.

5. The apparatus of claim 1, further comprising:

an insulative cap disposed upon a top nanosheet of the plurality of nanosheets;

an interlayer dielectric layer disposed upon the insulative cap; and

at least one contact formed within the interlayer dielectric layer and the insulative cap in contact with the source/drain epitaxy.

6. An apparatus, comprising:

a substrate structure having a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers, the substrate structure including at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate;

a u-shaped portion formed at a bottom portion of the at least one trench, the u-shaped portion including a bottom cavity;

a first liner disposed upon the u-shaped portion of the at least one trench;

a second liner disposed on the first liner;

a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity;

a plurality of recesses disposed between the nanosheet layers, wherein the third liner is further disposed within the plurality of recesses to form a plurality of inner spacers between the nanosheet layers;

a source/drain epitaxy disposed upon the bottom inner spacer;

a gate material disposed between the nanosheet layers;

an insulative cap disposed upon a top nanosheet of the plurality of nanosheets;

an interlayer dielectric layer disposed upon the insulative cap; and

at least one contact formed within the interlayer dielectric layer and the insulative cap in contact with the source/drain epitaxy.