Self-aligned gate cut in direct stacked vertical transport field effect transistor (VTFET)

• US 10,658,481 B1
• Filed: 10/29/2018
• Issued: 05/19/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Zhang, Chen, Yamashita, Tenko, Cheng, Kangguo, Miao, Xin
• Primary Examiner(s): Gebremariam, Samuel A
• Application Number:
  US16/173,532
• Publication Number:
  US 20200135877A1
• Time in Patent Office: 568 Days
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/76243 using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

Structures and/or methods that facilitate self-aligned gate cut on a dielectric fin extension in direct stacked vertical transport field effect transistor (VTFET). A semiconductor structure can comprise a silicon on insulator (SOI) semiconductor fin comprising a dielectric fin extension. The semiconductor structure can further comprise a first vertical transport field effect transistor (VTFET) comprising a first self-aligned gate on the dielectric fin extension. The semiconductor structure can further comprise a second VTFET comprising a second self-aligned gate on the dielectric fin extension. The semiconductor structure can further comprise a gate contact extending through the dielectric fin extension through the second VTFET to the first self-aligned gate.

Claims

1. A semiconductor structure, comprising:

a silicon on insulator (SOI) semiconductor fin comprising a dielectric fin extension;

a first vertical transport field effect transistor (VTFET) comprising a first self-aligned gate on the dielectric fin extension;

a second VTFET comprising a second self-aligned gate on the dielectric fin extension; and

a gate contact extending through the dielectric fin extension through the second VTFET to the first self-aligned gate.

2. The semiconductor structure of claim 1, further comprising a buried insulator disposed between an SOI wafer separating an SOI layer and a substrate layer.

3. The semiconductor structure of claim 2, further comprising a first dielectric fill patterned into the SOI wafer extending through the SOI layer, the buried insulator and partway through the substrate layer.

4. The semiconductor structure of claim 3, further comprising a hardmask disposed on the SOI layer, wherein the hardmask is used to pattern a hybrid fin comprising a semiconductor fin end and a dielectric fin end, wherein the dielectric fin end comprises the first dielectric fill and serves as the dielectric fin extension extending the length of the SOI semiconductor fin.

5. The semiconductor structure of claim 4, wherein the substrate layer serves as the first vertical fin channel for the first VTFET and the SOI layer serves as the second vertical fin channel for the second VTFET.

6. The semiconductor structure of claim 5, further comprising a first source and drain and a second source and drain over ends of the first vertical fin channel and a third source and drain and a fourth source and drain over ends of the second vertical fin channel.

7. The semiconductor structure of claim 6, wherein the first source and drain is formed on a base of the hybrid fin, wherein the second source and drain is formed by a first doped layer, wherein the third source and drain is formed by a second doped layer, and wherein the fourth source and drain is formed by the third doped layer.

8. The semiconductor structure of claim 7, further comprising a first spacer and a second spacer over the ends of the first vertical fin channel and a third spacer and a fourth spacer over the ends of the second vertical fin channel, wherein the first spacer is disposed on the first source and drain, the first doped layer is disposed on the second spacer, the third spacer is disposed on the second doped layer and the third doped layer is disposed on the fourth spacer.

9. The semiconductor structure of claim 8, wherein the first self-aligned gate is formed over the hybrid fin and etched back along a self-aligned horizontal surface of the hardmask and along a self-aligned horizontal surface the first spacer, and the second self-aligned gate is formed over the hybrid fin and etched back along a self-aligned horizontal surface of the hardmask and along a self-aligned horizontal surface of the third spacer.

10. The semiconductor structure of claim 9, further comprising a first interlayer dielectric and a second interlayer dielectric, wherein the first interlayer dielectric is disposed between and separates the first spacer and the second spacer, and the second interlayer dielectric is disposed between and separates the third spacer and the fourth spacer.

11. The semiconductor structure of claim 10, wherein the first self-aligned gate is further etched back along a self-aligned horizontal surface of the first interlayer dielectric, and the second self-aligned gate is further etched back along a self-aligned horizontal surface of the second interlayer dielectric.

12. The semiconductor structure of claim 3, further comprising an isolation spacer, wherein the isolation spacer is disposed alongside the buried insulator and separates the first VTFET and the second VTFET.

13. The semiconductor structure of claim 8, further comprising a second dielectric fill disposed alongside the hardmask and on the fourth doped layer.

14. The semiconductor structure of claim 13, wherein the gate contact extends through the second dielectric fill, the fourth doped layer, the fourth spacer, the second interlayer dielectric, the second self-aligned gate, the third spacer, the second doped layer, the isolation spacer, the first doped layer, the second spacer and stopping at the first interlayer dielectric and the first self-aligned gate.

15. The semiconductor structure of claim 14, wherein the gate contact accesses the second source and drain of the first VTFET.

16. A method, comprising:

forming a silicon on insulator (SOI) semiconductor fin comprising a dielectric fin extension;

forming a first vertical transport field effect transistor (VTFET) comprising a first self-aligned gate on the dielectric fin extension;

forming a second VTFET comprising a second self-aligned gate on the dielectric fin extension; and

forming a gate contact extending through the dielectric fin extension through the second VTFET to the first self-aligned gate.

17. The method of claim 16, further comprising using a gate contact mask to etch a contact trench and filling the contact trench with contact metal to form the gate contact.

18. The method of claim 16, wherein the gate contact accesses a source and drain of the first VTFET.

19. A method, comprising:

forming a dielectric fin extension on a silicon on insulator (SOI) wafer;

forming a first vertical transport field effect transistor (VTFET) and a second VTFET on an SOI semiconductor fin comprising the dielectric fin extension; and

forming a gate contact extending through the dielectric fin extension through the second VTFET to a self-aligned gate of the first VTFET.

20. The method of claim 19, wherein the gate contact accesses a source and drain of the first VTFET.