Mitigation of time dependent dielectric breakdown

• US 10,658,486 B2
• Filed: 05/18/2017
• Issued: 05/19/2020
• Est. Priority Date: 05/18/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Yi-Jyun, Young, Bao-Ru, Hsieh, Tung-Heng
• Primary Examiner(s): Wilczewski, Mary A
• Application Number:
  US15/599,045
• Publication Number:
  US 20180337053A1
• Time in Patent Office: 1,097 Days
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66871 Processes wherein the final gate is made after the formation of the source and drain regions in the active layer, e.g. dummy-gate processes
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.

Claims

1. A method, comprising:

forming a dielectric layer with an opening;

forming a multilayer gate metal stack in the opening to cover sidewalls of the opening and a top surface of the dielectric layer;

depositing a spacer layer on the multilayer gate metal stack;

etching the spacer layer with an anisotropic etchback process to form spacers on portions of the multilayer gate metal stack covering the sidewalls of the opening;

depositing a metal on the multilayer gate metal stack to fill the opening; and

after depositing the metal, planarizing the top surface of the dielectric layer to remove the multilayer gate metal stack and the metal from the top surface of the dielectric layer.

2. The method of claim 1, wherein the forming the multilayer gate metal stack comprises:

depositing a high-k dielectric in the opening to cover the sidewalls of the opening and the top surface of the dielectric layer; and

depositing a gate metal layer on the high-k dielectric.

3. The method of claim 2, wherein the gate metal layer comprises a capping layer, one or more metallic layers, and a work function metal stack.

4. The method of claim 1, wherein the depositing the spacer layer comprises depositing the spacer layer using a chemical vapor deposition (CVD), an atomic layer deposition (ALD), or a plasma-enhanced CVD (PECVD) process.

5. The method of claim 1, wherein the metal comprises a titanium nitride (TiN) layer and a tungsten (W) metal stack.

6. The method of claim 1, further comprising polishing a portion of the metal to remove a portion of the spacer layer to form a planar top surface of the spacer layer.

7. The method of claim 1, wherein depositing the metal comprises forming the metal with substantially linear side surfaces.

8. A structure, comprising:

a substrate;

two opposing spacers on the substrate;

a first dielectric disposed over the substrate between the two opposing spacers;

a second dielectric conformally deposited between the two opposing spacers and over the first dielectric;

a multilayer gate metal stack conformally deposited over the second dielectric, wherein the multilayer gate metal stack comprises a first recess with side surfaces and a bottom surface between the side surfaces, wherein the side surfaces and the bottom surface expose a topmost layer of the multilayer gate metal stack;

a spacer layer disposed over the side surfaces of the first recess to form a second recess smaller than the first recess, wherein the spacer layer comprises a third dielectric; and

a metal deposited into the second recess.

9. The structure of claim 8, wherein the spacer layer has a thickness range up to 2.5 nm.

10. The structure of claim 8, wherein:

the first dielectric comprises an interfacial oxide;

the second dielectric comprises a high-k dielectric; and

the third dielectric comprises silicon nitride (Si₃N₄), silicon oxynitride (SiON), carbon-doped silicon nitride (SiCN), or silicon oxycarbide (SiO_xC_y).

11. The structure of claim 8, wherein the first recess comprises an aperture between 10 nm and 15 nm, and the second recess comprises an aperture up to 5 nm.

12. The structure of claim 8, wherein the multilayer gate metal stack comprises a capping layer, one or more metallic layers, and a work function metal stack.

13. The structure of claim 8, wherein the spacer layer comprises a planar top surface.

14. The structure of claim 8, wherein the metal comprises substantially linear side surfaces.

15. The structure of claim 8, wherein the spacer layer is separated from the two opposing spacers by the second dielectric and the multilayer metal gate stack.

16. A method, comprising:

providing a substrate;

forming two opposing spacers on the substrate;

forming a first dielectric over the substrate between the two opposing spacers;

depositing a second dielectric between the two opposing spacers and over the first dielectric;

depositing a multilayer gate metal stack over the second dielectric and over sides of the two opposing spacers to form a first recess with side surfaces;

depositing a spacer layer over the side surfaces of the first recess to form a second recess smaller than the first recess, wherein the spacer layer comprises a third dielectric; and

depositing a metal into the second recess.

17. The method of claim 16, wherein depositing the spacer layer comprises forming the spacer layer using a chemical vapor deposition (CVD), an atomic layer deposition (ALD), or a plasma-enhanced CVD (PECVD) process.

18. The method of claim 16, wherein forming the spacer layer comprises forming the spacer layer using an anisotropic etchback process with a carbon fluoride (CF_x) based chemistry and an etch rate up to 5 Å

/sec.

19. The method of claim 16, further comprising removing a portion of the metal and a portion of the multilayer gate metal stack to coplanarize a top surface of the metal and another top surface of the multilayer gate metal stack.

20. The method of claim 16, wherein the depositing the spacer layer over the side surfaces of the first recess comprises:

depositing the third dielectric into the first recess; and

anisotropically etching a portion of the deposited third dielectric to form the spacer layer having substantially vertical side surfaces.