Controlling profiles of replacement gates

• US 10,658,491 B2
• Filed: 06/15/2018
• Issued: 05/19/2020
• Est. Priority Date: 06/15/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chih-Han, Kao, Kuei-Yu, Chang, Ming-Ching, Yang, Chan-Lon, Chen, Chao-Cheng, Jang, Syun-Ming
• Primary Examiner(s): Vu, Hung K
• Application Number:
  US16/009,793
• Publication Number:
  US 20190386115A1
• Time in Patent Office: 704 Days
• Field of Search: None
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method includes forming a dummy gate electrode layer over a semiconductor region, forming a mask strip over the dummy gate electrode layer, and performing a first etching process using the mask strip as a first etching mask to pattern an upper portion of the dummy gate electrode layer. A remaining portion of the upper portion of the dummy gate electrode layer forms an upper part of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper part of the dummy gate electrode, and performing a second etching process on a lower portion of the dummy gate electrode layer to form a lower part of the dummy gate electrode, with the protection layer and the mask strip in combination used as a second etching mask. The dummy gate electrode and an underlying dummy gate dielectric are replaced with a replacement gate stack.

Claims

1. A method comprising:

forming a dummy gate electrode layer over a semiconductor region;

forming a mask strip over the dummy gate electrode layer;

performing a first etching process using the mask strip as a first etching mask to pattern an upper portion of the dummy gate electrode layer, with a remaining portion of the upper portion of the dummy gate electrode layer forming an upper part of a dummy gate electrode;

forming a protection layer on sidewalls of the upper part of the dummy gate electrode;

performing a second etching process on a lower portion of the dummy gate electrode layer to form a lower part of the dummy gate electrode, wherein the protection layer and the mask strip in combination are used as a second etching mask; and

replacing the dummy gate electrode and an underlying dummy gate dielectric with a replacement gate stack.

2. The method of claim 1, wherein the lower portion of the dummy gate electrode layer is etched in a process comprising:

etching the lower portion until an isolation region underlying the dummy gate electrode layer is revealed; and

trimming the lower part of the dummy gate electrode to have a tapered profile.

3. The method of claim 1, wherein sidewalls of the upper part of the dummy gate electrode are substantially straight, and sidewalls of the lower part of the dummy gate electrode are more slanted than the upper part of the dummy gate electrode.

4. The method of claim 1, wherein the semiconductor region comprises a semiconductor fin protruding higher than top surfaces of isolation regions on opposite sides of the semiconductor fin, and an interface of the upper part and the lower part of the dummy gate electrode is higher than a top surface of the semiconductor fin.

5. The method of claim 1, wherein the semiconductor region comprises a semiconductor fin protruding higher than top surfaces of isolation regions on opposite sides of the semiconductor fin, and an interface of the upper part and the lower part of the dummy gate electrode is lower than a top surface of the semiconductor fin.

6. The method of claim 1, wherein after the replacing, the replacement gate stack is encircled by the protection layer.

7. The method of claim 1 further comprising removing the protection layer.

8. The method of claim 1 further comprising forming an inter-layer dielectric over the protection layer and the dummy gate electrode therein, wherein the replacing comprises:

etching the dummy gate electrode to form a trench in the inter-layer dielectric; and

removing the protection layer from the trench.

9. A method comprising:

forming isolation regions extending into a semiconductor substrate;

forming a semiconductor fin protruding higher than the isolation regions;

forming a dummy gate dielectric on the semiconductor fin;

forming a dummy gate electrode layer over the dummy gate dielectric;

performing a first etching process on an upper portion of the dummy gate electrode layer, wherein the first etching process is stopped when a top surface of a lower portion of the dummy gate electrode layer is at an intermediate level between a top surface and a bottom surface of the dummy gate electrode layer;

depositing a protection layer;

removing horizontal portions of the protection layer, with a vertical portion of the protection layer encircling a remaining upper portion of the dummy gate electrode layer; and

performing a second etching process to etch the lower portion of the dummy gate electrode layer, with the protection layer protecting the remaining upper portion of the dummy gate electrode layer during the second etching process.

10. The method of claim 9 further comprising replacing the remaining upper portion and a remaining lower portion of the dummy gate electrode layer and the dummy gate dielectric with a replacement gate stack.

11. The method of claim 10, wherein the protection layer has sidewalls contacting sidewalls of the replacement gate stack.

12. The method of claim 9 further comprising removing the protection layer.

13. The method of claim 9, wherein when the first etching process is stopped, the dummy gate dielectric is embedded in the lower portion of the dummy gate electrode layer.

14. The method of claim 9, wherein when the first etching process is stopped, the dummy gate dielectric is exposed.

15. The method of claim 9 further comprising forming a gate spacer, wherein the protection layer has a bottom surface higher than a bottom surface of the gate spacer.

16. A method comprising:

forming a polysilicon layer;

performing a first etching process on the polysilicon layer, with a remaining portion of the polysilicon layer forming a polysilicon strip as a result of the first etching process, wherein the first etching process comprises;

etching an upper portion of the polysilicon layer;

forming a protection layer on a top surface and sidewalls of a remaining portion of the upper portion of the polysilicon layer; and

after the protection layer is formed, etching a lower portion of the polysilicon layer;

performing a second etching process on the polysilicon strip to make sidewalls of the lower portion of the polysilicon strip to be more tapered than before the second etching process, wherein the upper portion of the polysilicon strip is protected from the second etching process; and

forming dielectric layers embedding the polysilicon strip therein.

17. The method of claim 16, wherein the lower portion of the polysilicon strip has bottom portions being increasingly narrower than respective upper portions of the lower portion of the polysilicon strip.

18. The method of claim 16, wherein the protection layer is a conformal layer.

19. The method of claim 16, wherein the polysilicon layer is formed on a semiconductor fin, and in the first etching process and the second etching process, the semiconductor fin is protected by an additional dielectric layer.

20. The method of claim 16, wherein the etching the lower portion of the polysilicon layer is performed with a first bias power, and the second etching process is performed with a second bias power lower than the first bias power.