Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates

• US 10,658,493 B2
• Filed: 07/18/2019
• Issued: 05/19/2020
• Est. Priority Date: 04/03/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bi, Zhenxing, Cheng, Kangguo, Loubet, Nicolas J., Miao, Xin, Xu, Wenyu, Zhang, Chen
• Primary Examiner(s): Harriston, William A
• Application Number:
  US16/515,759
• Publication Number:
  US 20190341465A1
• Time in Patent Office: 306 Days
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Embodiments of the invention are directed to a nano sheet field effect transistor (FET) device that includes a gate spacer and an inner spacer. The gate spacer includes an upper segment and a lower segment. The inner spacer has a first selectivity to etch compositions used in predetermined fabrication operations for forming the inner spacer. The lower segment has the first selectivity to etch compositions used in predetermined fabrication operations for forming the inner spacer. The upper segment has a second selectivity to etch compositions used in predetermined fabrication operations for forming the inner spacer. The first etch selectivity is greater than the second etch selectivity.

Claims

1. A nanosheet field effect transistor (FET) device comprising:

a gate spacer; and

an inner spacer;

wherein the gate spacer comprises an upper segment and a lower segment;

wherein the inner spacer has a first selectivity to etch compositions used in predetermined fabrication operations for forming the lower segment and the inner spacer;

wherein the lower segment has the first selectivity to the etch compositions used in the predetermined fabrication operations for forming the lower segment and the inner spacer;

wherein the upper segment has a second selectivity to etch compositions used in the predetermined fabrication operations for forming the lower segment and the inner spacer; and

wherein the first etch selectivity is greater than the second etch selectivity such that the upper segment functions as a first mask in the predetermined fabrication operations for forming the lower segment.

2. The device of claim 1, wherein the gate spacer is formed on a sidewall of a gate region of the nanosheet FET.

3. The device of claim 2, wherein the upper segment is positioned above the lower segment.

4. The device of claim 3, wherein:

the inner spacer is formed between channel nanosheets of the nanosheet FET;

the channel nanosheets have a third selectivity to etch compositions used in predetermined fabrication operations for forming the lower segment and the inner spacer; and

the first etch selectivity is greater than third etch selectivity such that the channel nanosheets function as a second mask in the predetermined fabrication operations for forming the inner spacers.

5. The device of claim 4, wherein the inner spacer comprises a first material.

6. The device of claim 5, wherein the lower segment comprises the first material.

7. The device of claim 6, wherein the first material comprises the first etch selectivity.

8. The device of claim 7, wherein the upper segment comprises a second material.

9. The device of claim 8, wherein the second material comprises the second etch selectivity.

10. The device of claim 9, wherein:

the first material comprises a first type of low-k material; and

the second material comprises a second type of low-k material.

11. A nanosheet field effect transistor (FET) device comprising:

gate spacers; and

inner spacers;

wherein each of the gate spacers comprises an upper segment and a lower segment;

wherein the inner spacers have a first selectivity to etch compositions used in predetermined fabrication operations for forming the lower segment and the inner spacers;

wherein the lower segments have the first selectivity to the etch compositions used in the predetermined fabrication operations for forming the lower segment and the inner spacers;

wherein the upper segments have a second selectivity to the etch compositions used in the predetermined fabrication operations for forming the lower segment and the inner spacers; and

wherein the first etch selectivity is greater than the second etch selectivity such that the upper segment functions as a first mask in the predetermined fabrication operations for forming the lower segment.

12. The device of claim 11, wherein the gate spacers are formed on sidewalls of a gate region of the nanosheet FET.

13. The device of claim 12, wherein each of the upper segments is positioned above one of the lower segments.

14. The device of claim 13, wherein:

the inner spacers are formed between channel nanosheets of the nanosheet FET;

the channel nanosheets have a third selectivity to etch compositions used in predetermined fabrication operations for forming the lower segment and the inner spacers; and

the first etch selectivity is greater than third etch selectivity such that the channel nanosheets function as a second mask in the predetermined fabrication operations for forming the inner spacers.

15. The device of claim 14, wherein the inner spacers comprises a first material.

16. The device of claim 15, wherein the lower segments comprise the first material.

17. The device of claim 16, wherein the first material comprises the first etch selectivity.

18. The device of claim 17, wherein the upper segments comprise a second material.

19. The device of claim 18, wherein the second material comprises the second etch selectivity.

20. The device of claim 19, wherein:

the first material comprises a first type of low-k material; and

the second material comprises a second type of low-k material.