Automatic power over ethernet pulse width signaling correction

• US 10,659,241 B2
• Filed: 08/20/2019
• Issued: 05/19/2020
• Est. Priority Date: 02/07/2017
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Picard, Jean
• Primary Examiner(s): Luque, Renan
• Application Number:
  US16/545,130
• Publication Number:
  US 20190372789A1
• Time in Patent Office: 273 Days
• CPC Class Codes: H02J 3/02 using a single network for simultaneous distribution of power at different frequencies; using a single network for simultaneous distribution of ac power and of dc power
• CPC Class Codes: H04L 12/10 Current supply arrangements
• CPC Class Codes: H05B 45/32 Pulse-control circuits
• CPC Class Codes: H05B 45/50 responsive to malfunctions or undesirable behaviour of LEDs; responsive to LED life; Protective circuits
• CPC Class Codes: H05B 47/18 via data-bus transmission

Abstract

In a Power over Ethernet (PoE) system, a Powered Device (PD) having circuitry to measure the load current from a Power Sourcing Equipment (PSE) in the PD. Circuitry compares the measured load current with a first threshold. Circuitry automatically generates load pulses for signaling the PSE. The pulse widths of the load pulses are measured and the widths are automatically adjusted, that power to the PD should be maintained.

Claims

1. A powered device (PD) for use in a power over Ethernet (PoE) system, the PD device comprising:

first and second voltage supply terminals associated with the PoE system;

a return terminal associated with a load;

a detection circuit configured to generate a maintain power signature (MPS) enable signal upon detecting a load current, between the return terminal and the second voltage supply terminal, to be less than a first MPS reference threshold;

a MPS generation circuit configured to generate a MPS pulse upon receiving the MPS enable signal, the MPS generation circuit configured to regulate an amplitude of the MPS pulse based on a second MPS reference threshold and to regulate a duration of the MPS pulse based on the second MPS reference threshold extended by a predetermined time period after the MPS pulse reaches an active-high level.

2. The PD device of claim 1, wherein:

the first voltage supply terminal is configured to receive a first voltage VDD from a power supply equipment (PSE) of the PoE system;

the second voltage supply terminal is configured to receive a second voltage VSS from the PSE of the PoE system; and

the return terminal is configured to receive a ground voltage from the load.

3. The PD device of claim 1, wherein:

the first MPS reference threshold includes an automatic MPS (AutoMPS) reference voltage in compliant with IEEE 802.3-2012 and IEEE 802.3bt; and

the second MPS reference threshold includes an MPS current reference voltage in compliant with IEEE 802.3-2012 and IEEE 802.3bt.

4. The PD device of claim 1, wherein the second MPS reference threshold is greater than the first MPS reference threshold.

5. The PD device of claim 1, wherein the detection circuit includes:

an amplifier stage coupled between the return terminal and the second voltage supply terminal, and having a sense node configured to develop a sense voltage representative of the load current; and

a comparator having a non-inverting input coupled to the sense node, an inverting input coupled to receive the first MPS reference threshold, and an output configured to deliver the MPS enable signal.

6. The PD device of claim 5, wherein the amplifier stage includes:

a transistor coupled between the return terminal and the sense node; and

a resistor coupled between the sense node and the second voltage supply terminal.

7. The PD device of claim 6, wherein the amplifier stage includes:

an error amplifier having a non-inverting input coupled to receive a current limit reference, an inverting input coupled to the sense node, and an output coupled to a gate terminal of the transistor.

8. The PD device of claim 5, wherein the MPS generation circuit includes:

a transistor coupled between the first voltage supply terminal and an MPS node configured to output the MPS pulse;

a resistor coupled having a first terminal coupled to the MPS node, and a second terminal coupled to the sense node;

a differential amplifier having a first input coupled to the first terminal, a second input coupled to the second terminal, and an amplified output; and

a correction circuit having a first input coupled to the amplified output, a second input coupled to receive the second MPS reference threshold, and a correction output coupled to a gate of the transistor.

9. The PD device of claim 1, wherein the detection circuit include:

a first stage coupled between the return terminal and the second voltage supply terminal, and configured to develop, at a sense node, a first sense voltage representative of the load current when the first stage is enabled;

a second stage coupled between the return terminal and the second voltage supply terminal, and configured to develop, at the sense node, a second sense voltage representative of the load current when the second stage is enabled; and

a timing logic configured to enable the first stage and disable the second stage when the MPS enable signal is absent, and configured to disable the first stage and enable the second stage when the MPS enable signal is generated.

10. The PD device of claim 9, wherein:

the first stage includes a first transistor coupled between the return terminal and the sense node, and a first resistor coupled between the sense node and the second voltage supply terminal; and

the second stage includes a second transistor coupled between the return terminal and an MPS node, and a second resistor coupled between the MPS node and the sense node.

11. The PD device of claim 10, wherein the detection circuit includes:

an error amplifier having a non-inverting input coupled to receive a current limit reference, an inverting input coupled to the sense node, and an output;

a first switch coupled between the output of the error amplifier and a first gate of the first transistor, the first switch configured to be closed by the timing logic when the MPS enable signal is absent; and

a second switch coupled between the output of the error amplifier and a second gate of the second transistor, the second switch configured to be closed by the timing logic when the MPS enable signal is generated.

12. The PD device of claim 11, wherein the detection circuit includes:

a third switch coupled between the first gate of the first transistor and the second voltage supply terminal, the third switch configured to be closed by the timing logic when the MPS enable signal is generated; and

a fourth switch coupled between the second gate of the second transistor and the sense node, the third switch configured to be closed by the timing logic when the MPS enable signal is absent.

13. The PD device of claim 10, wherein the MPS generation circuit includes:

a third transistor coupled between the first voltage supply terminal and the MPS node configured to output the MPS pulse; and

an amplifier having a non-inverting input coupled to receive the second MPS reference threshold, an inverting input coupled to the MPS node, and an output coupled to a third gate of the third transistor.

14. The PD device of claim 9, wherein the detection circuit includes:

a comparator having a non-inverting input coupled to the sense node, an inverting input coupled to receive the first MPS reference threshold, and an output configured to assert the MPS enable signal.

15. An integrated circuit (IC) for use in a powered device (PD) of a power over Ethernet (PoE) system, the IC comprising:

first and second voltage supply terminals associated with the PoE system;

a return terminal associated with a load;

a detection circuit including;

an amplifier stage having a sense node configured to develop a sense voltage representative of a load current between the return terminal and the second voltage supply terminal; and

a comparator having a non-inverting input coupled to the sense node, an inverting input coupled to receive a first maintain power signature (MPS) reference threshold, and an output configured to deliver an MPS enable signal; and

an MPS generation circuit configured to generate a MPS pulse between the first and second voltage supply terminals and upon receiving the MPS enable signal, the MPS generation circuit configured to regulate an amplitude of the MPS pulse based on a second MPS reference threshold and to regulate a duration of the MPS pulse based on the second MPS reference threshold extended by a predetermined time period after the MPS pulse reaches an active-high level.

16. The IC of claim 15, wherein the amplifier stage includes:

a transistor coupled between the return terminal and the sense node;

a resistor coupled between the sense node and the second voltage supply terminal; and

an error amplifier having a non-inverting input coupled to receive a current limit reference, an inverting input coupled to the sense node, and an output coupled to a gate terminal of the transistor.

17. The IC of claim 15, wherein the MPS generation circuit includes:

a transistor coupled between the first voltage supply terminal and an MPS node configured to output the MPS pulse;

a resistor coupled between the MPS node and the second voltage supply terminal; and

an amplifier having a non-inverting input coupled to receive the second MPS reference threshold, an inverting input coupled to the MPS node, and an output coupled to a gate terminal of the transistor.

18. An integrated circuit (IC) for use in a powered device (PD) of a power over Ethernet (PoE) system, the IC comprising:

first and second voltage supply terminals associated with the PoE system;

a return terminal associated with a load;

a first stage includes a first transistor coupled between the return terminal and a sense node, and a first resistor coupled between the sense node and the second voltage supply terminal;

a second stage includes a second transistor coupled between the return terminal and an MPS node, and a second resistor coupled between the MPS node and the sense node;

a comparator configured to assert a maintain power signature (MPS) enable signal when a sense voltage at the sense node is less than a first MPS reference threshold, and configured to reset the MPS enable signal when the sense voltage is greater than the first MPS reference threshold;

a timing logic configured to enable the first stage and disable the second stage when the MPS enable signal is reset, and configured to disable the first stage and enable the second stage when the MPS enable signal is asserted; and

a MPS generation circuit configured to generate a MPS pulse, at the MPS node, upon receiving the MPS enable signal, the MPS generation circuit configured to regulate an amplitude of the MPS pulse based on a second MPS reference threshold and to regulate a duration of the MPS pulse based on the second MPS reference threshold extended by a predetermined time period after the MPS pulse reaches an active-high level.

19. The IC of claim 18, further comprising:

an error amplifier having a non-inverting input coupled to receive a current limit reference, an inverting input coupled to the sense node, and an output;

a first switch coupled between the output of the error amplifier and a first gate of the first transistor, the first switch configured to be closed by the timing logic when the MPS enable signal is reset;

a second switch coupled between the output of the error amplifier and a second gate of the second transistor, the second switch configured to be closed by the timing logic when the MPS enable signal is asserted;

a third switch coupled between the first gate of the first transistor and the second voltage supply terminal, the third switch configured to be closed by the timing logic when the MPS enable signal is asserted; and

a fourth switch coupled between the second gate of the second transistor and the sense node, the third switch configured to be closed by the timing logic when the MPS enable signal is reset.

20. The IC of claim 18, wherein the MPS generation circuit includes:

a third transistor coupled between the first voltage supply terminal and the MPS node configured to output the MPS pulse; and

an amplifier having a non-inverting input coupled to receive the second MPS reference threshold, an inverting input coupled to the MPS node, and an output coupled to a third gate of the third transistor.