DC coefficient signaling at small quantization step sizes

• US 10,659,793 B2
• Filed: 08/10/2018
• Issued: 05/19/2020
• Est. Priority Date: 07/18/2003
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Lin, Chih-Lung, Regunathan, Shankar, Srinivasan, Sridhar
• Primary Examiner(s): Anyikire, Chikaodili E
• Application Number:
  US16/101,173
• Publication Number:
  US 20180352238A1
• Time in Patent Office: 648 Days
• Field of Search: None
• CPC Class Codes: H04N 19/124 Quantisation
• CPC Class Codes: H04N 19/126 Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers
• CPC Class Codes: H04N 19/136 Incoming video signal characteristics or properties
• CPC Class Codes: H04N 19/137 Motion inside a coding unit, e.g. average field, frame or block difference
• CPC Class Codes: H04N 19/17 the unit being an image region, e.g. an object
• CPC Class Codes: H04N 19/176 the region being a block, e.g. a macroblock
• CPC Class Codes: H04N 19/18 the unit being a set of transform coefficients
• CPC Class Codes: H04N 19/184 the unit being bits, e.g. of the compressed video stream
• CPC Class Codes: H04N 19/186 the unit being a colour or a chrominance component
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/46 Embedding additional information in the video signal during the compression process H04N19/517, H04N19/68, H04N19/70 take precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/625 using discrete cosine transform [DCT]
• CPC Class Codes: H04N 19/70 characterised by syntax aspects related to video coding, e.g. related to compression standards
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

Described tools and techniques relate to signaling for DC coefficients at small quantization step sizes. The techniques and tools can be used in combination or independently. For example, a tool such as a video encoder or decoder processes a VLC that indicates a DC differential for a DC coefficient, a FLC that indicates a value refinement for the DC differential, and a third code that indicates the sign for the DC differential. Even with the small quantization step sizes, the tool uses a VLC table with DC differentials for DC coefficients above the small quantization step sizes. The FLCs for DC differentials have lengths that vary depending on quantization step size.

Claims

1. A method comprising:

receiving encoded data in a bitstream; and

decoding the encoded data to reconstruct a picture, including, for a block of the picture;

determining a quantization step size that applies for the block based on one or more syntax elements in the bitstream;

decoding a variable length code (VLC) for a DC differential for a DC coefficient of the block, the DC differential representing a difference between the DC coefficient and a DC predictor for the DC coefficient of the block, wherein the decoding the VLC uses a VLC table that includes an escape code as well as different VLC values that are associated with different values for DC differentials, and wherein the VLC is not the escape code, such that the decoding the VLC yields a value for the DC differential for the DC coefficient of the block;

checking whether the quantization step size that applies for the block is one of a set of small quantization step sizes; and

reconstructing the DC differential, including using the value for the DC differential for the DC coefficient of the block as a base absolute value or as a final absolute value depending on whether the quantization step size that applies for the block is one of the set of small quantization step sizes.

2. The method of claim 1, wherein the quantization step size that applies for the block is one of the set of small quantization step sizes if the quantization step size that applies for the block is 1 or 2.

3. The method of claim 1, wherein the decoding the encoded data further includes:

determining that the quantization step size that applies for the block is one of the set of small quantization step sizes; and

decoding a fixed length code (FLC) that indicates a refinement value for the DC differential for the DC coefficient of the block, wherein the reconstructing the DC differential uses the base absolute value, the refinement value, and a sign value.

4. The method of claim 3, wherein the FLC has a length that varies depending on the quantization step size that applies for the block.

5. The method of claim 4, wherein:

if the quantization step size that applies for the block is 1, the length of the FLC is 2; and

if the quantization step size that applies for the block is 2, the length of the FLC is 1.

6. The method of claim 1, wherein the decoding the encoded data further includes:

determining that the quantization step size that applies for the block is not one of the set of small quantization step sizes, wherein the reconstructing the DC differential uses the final absolute value and a sign value.

7. The method of claim 1, wherein the decoding the encoded data further includes:

computing the DC predictor; and

combining the DC differential and the DC predictor.

8. The method of claim 1, wherein the VLC table further includes:

a VLC associated with a zero value.

9. The method of claim 1, wherein the one or more blocks are intra-coded blocks.

10. The method of claim 1, wherein the quantization step size that applies for the block is indicated at least in part by a picture-layer syntax element for the picture and at least in part by a differential quantization syntax element that adjusts the quantization step size for a macroblock that includes the block.

11. One or more computer-readable memory devices storing computer-executable instructions for causing one or more processing units, when programmed thereby, to perform operations comprising:

receiving encoded data in a bitstream; and

decoding the encoded data to reconstruct a picture, including, for a block of the picture;

determining a quantization step size that applies for the block based on one or more syntax elements in the bitstream;

decoding a variable length code (VLC) for a DC differential for a DC coefficient of the block, the DC differential representing a difference between the DC coefficient and a DC predictor for the DC coefficient of the block, wherein the decoding the VLC uses a VLC table that includes an escape code as well as different VLC values that are associated with different values for DC differentials, and wherein the VLC is not the escape code, such that the decoding the VLC yields a value for the DC differential for the DC coefficient of the block;

checking whether the quantization step size that applies for the block is one of a set of small quantization step sizes; and

reconstructing the DC differential, including using the value for the DC differential for the DC coefficient of the block as a base absolute value or as a final absolute value depending on whether the quantization step size that applies for the block is one of the set of small quantization step sizes.

12. The one or more computer-readable memory devices of claim 11, wherein the quantization step size that applies for the block is one of the set of small quantization step sizes if the quantization step size that applies for the block is 1 or 2.

13. The one or more computer-readable memory devices of claim 12, wherein the decoding the encoded data further includes:

determining that the quantization step size that applies for the block is one of the set of small quantization step sizes; and

decoding a fixed length code (FLC) that indicates a refinement value for the DC differential for the DC coefficient of the block, wherein the reconstructing the DC differential uses the base absolute value, the refinement value, and a sign value.

14. The one or more computer-readable memory devices of claim 13, wherein the FLC has a length that varies depending on the quantization step size that applies for the block.

15. The one or more computer-readable memory devices of claim 11, wherein the decoding the encoded data further includes:

determining that the quantization step size that applies for the block is not one of the set of small quantization step sizes, wherein the reconstructing the DC differential uses the final absolute value and a sign value.

16. The one or more computer-readable memory devices of claim 11, wherein the VLC table further includes a VLC associated with a zero value.

17. A computer system comprising:

a buffer configured to receive encoded data in a bitstream; and

a decoder configured to decode the encoded data to reconstruct a picture by performing operations that include, for a block of the picture;

determining a quantization step size that applies for the block based on one or more syntax elements in the bitstream;

decoding a variable length code (VLC) for a DC differential for a DC coefficient of the block, the DC differential representing a difference between the DC coefficient and a DC predictor for the DC coefficient of the block, wherein the decoding the VLC uses a VLC table that includes an escape code as well as different VLC values that are associated with different values for DC differentials, and wherein the VLC is not the escape code, such that the decoding the VLC yields a value for the DC differential for the DC coefficient of the block;

checking whether the quantization step size that applies for the block is one of a set of small quantization step sizes; and

reconstructing the DC differential, including using the value for the DC differential for the DC coefficient of the block as a base absolute value or as a final absolute value depending on whether the quantization step size that applies for the block is one of the set of small quantization step sizes.

18. The computer system of claim 17, wherein the operations further include:

determining that the quantization step size that applies for the block is one of the set of small quantization step sizes; and

decoding a fixed length code (FLC) that indicates a refinement value for the DC differential for the DC coefficient of the block, wherein the reconstructing the DC differential uses the base absolute value, the refinement value, and a sign value.

19. The computer system of claim 18, wherein the FLC has a length that varies depending on the quantization step size that applies for the block.

20. The computer system of claim 17, wherein the operations further include:

determining that the quantization step size that applies for the block is not one of the set of small quantization step sizes, wherein the reconstructing the DC differential uses the final absolute value and a sign value.