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Power efficient processor architecture

  • US 10,664,039 B2
  • Filed: 07/24/2018
  • Issued: 05/26/2020
  • Est. Priority Date: 09/06/2011
  • Status: Active Grant
First Claim
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1. A non-transitory computer readable storage medium comprising a set of instructions which, when executed by one or more processors, causes a mobile system to:

  • migrate a task from a second set of processor cores to a first set of processor cores when it is determined that a value, associated with execution duration of the task, exceeds a threshold timewherein;

    each processor core of the first set has a first size, and wherein the first set includes a first cache;

    each processor core of the second set has a second size, wherein the first size is larger than the second size, and wherein the second set includes a second cache; and

    the first set of processor cores is coupled to the second set of processor cores through an interconnect and via the first and second caches of the first and second set, respectively, wherein an operating system (OS) is aware of tasks to be scheduled on the first and second sets of processor cores, and wherein the OS is to use a history of the task to determine which one of the processor cores of the first or second set to wake up from a low power state.

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