Filtering coherency protocol transactions

• US 10,664,399 B2
• Filed: 11/29/2017
• Issued: 05/26/2020
• Est. Priority Date: 12/02/2016
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Persson, Hakan Lars-Goran, Bratt, Ian Rudolf, Swaine, Andrew Brookfield, Mathewson, Bruce James
• Primary Examiner(s): Yi, David
• Assistant Examiner(s): Fulford, Dustin B.
• Application Number:
  US15/825,633
• Publication Number:
  US 20180157590A1
• Time in Patent Office: 909 Days
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

A filter comprises interface circuitry, to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between the first cache and at least one other cache or other master device. The filter has filtering circuitry for filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.

Claims

1. An apparatus comprising:

a filter comprising;

interface circuitry to intercept coherency protocol transactions exchanged between a first master device and an interconnect for managing coherency between a first cache comprised by said first master device and at least one other cache or a second master device; and

filtering circuitry to filter the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the first master device is allowed to access;

wherein in response to an outgoing coherency protocol transaction issued from said first master device to said interconnect after a lookup in the first cache by the first master device, the filtering circuitry is configured to block the outgoing coherency protocol transaction when a memory access permission violation is detected for the outgoing coherency protocol transaction in dependence on the memory access permission data; and

wherein the filtering circuitry is configured to detect said memory access permission violation when the outgoing coherency protocol transaction is a read transaction capable of causing data to be stored in said first cache in a shareable modifiable coherency state in which coherency is to be maintained between the data in said first cache and said at least one other cache or the second master device, and the first master device is allowed to modify the data without issuing a further coherency protocol transaction to said interconnect, and the memory access permission data specifies that the first master device is;

prohibited from writing data to a region of the address space including a target address specified by the outgoing coherency protocol transaction; and

permitted to read data from said region of the address space including the target address specified by the outgoing coherency protocol transaction.

2. The apparatus according to claim 1, wherein the filtering circuitry is configured to filter snoop transactions exchanged between the first master device and the interconnect in dependence on the memory access permission data.

3. The apparatus according to claim 1, wherein the memory access permission data defines for a given region of the address space:

whether the first master device is allowed to read data from the given region; and

whether the first master device is allowed to write data to the given region.

4. The apparatus according to claim 1, wherein the filtering circuitry is configured to block the outgoing coherency protocol transaction by triggering an error condition when the memory access permission violation is detected for the outgoing coherency protocol transaction.

5. The apparatus according to claim 1, wherein the filtering circuitry is configured to block the outgoing coherency protocol transaction by:

returning dummy data to said first master device when the outgoing coherency protocol transaction is a read transaction; and

preventing write data associated with the outgoing coherency protocol transaction being passed to said at least one other cache or the second master device or a memory when the outgoing coherency protocol transaction is a write transaction.

6. The apparatus according to claim 1, wherein the filtering circuitry is configured to block the outgoing coherency protocol transaction by replacing the outgoing coherency protocol transaction with an alternative coherency protocol transaction.

7. The apparatus according to claim 1, wherein the filtering circuitry is configured to detect said memory access permission violation when the outgoing coherency protocol transaction is a read transaction and the memory access permission data specifies that the first master device is prohibited from reading data from a region of the address space including a target address specified by the read transaction.

8. The apparatus according to claim 1, wherein the filtering circuitry is configured to detect said memory access permission violation when the outgoing coherency protocol transaction is a write transaction and the memory access permission data specifies that the first master device is prohibited from writing data to a region of the address space including a target address specified by the write transaction.

9. The apparatus according to claim 1, wherein the filtering circuitry is configured to detect said memory access permission violation when the outgoing coherency protocol transaction is a transaction, other than a write transaction, which is capable of triggering invalidation of data in said at least one other cache, and the memory access permission data specifies that the first master device is prohibited from writing data to a region of the address space including a target address specified by the outgoing coherency protocol transaction.

10. The apparatus according to claim 1, wherein the filtering circuitry is configured to detect said memory access permission violation when the outgoing coherency protocol transaction is capable of causing dirty data to be stored in said first cache, and the memory access permission data specifies that the first master device is prohibited from writing data to a region of the address space including a target address specified by the outgoing coherency protocol transaction.

11. The apparatus according to claim 1, wherein the filtering circuitry is configured to block an incoming coherency protocol transaction issued from said interconnect to said first master device, when a memory access permission violation is detected for the incoming coherency protocol transaction in dependence on said memory access permission data.

12. The apparatus according to claim 11, wherein the filtering circuitry is configured to block the incoming coherency protocol transaction by preventing the incoming coherency protocol transaction being passed to said first master device.

13. The apparatus according to claim 11, wherein the filtering circuitry is configured to block the incoming coherency protocol transaction by replacing the incoming coherency protocol transaction with an invalidating coherency protocol transaction for triggering invalidation from the first cache of any data associated with the target address specified by the incoming coherency protocol transaction.

14. The apparatus according to claim 11, wherein the filtering circuitry is configured to return a miss response to the interconnect in response to the blocked incoming coherency protocol transaction, the miss response indicating that a target address specified by the incoming coherency protocol transaction missed in the first cache.

15. The apparatus according to claim 11, wherein the filtering circuitry is configured to block an incoming coherency protocol transaction when the memory access permission data specifies that the first master device is prohibited from reading data from a region of the address space including a target address specified by the incoming coherency protocol transaction or is prohibited from writing data to said region of the address space including said target address.

16. The apparatus according to claim 1, wherein the filtering circuitry is configured to lookup the memory access permission data in dependence on a target address of a coherency protocol transaction received from one of the first master device and the interconnect, and control issuing of a coherency protocol transaction specifying said target address to whichever of the first master device and the interconnect was not referenced as the one of the first master device and the interconnect in dependence on the looked up memory access permission data.

17. The apparatus according to claim 1, wherein the filtering circuitry is configured to lookup the memory access permission data in dependence on a target address of a coherency protocol transaction received from one of the first master device and the interconnect, map the target address to a translated address in dependence on address translation data, and

control issuing of a coherency protocol transaction specifying said translated address to the other of the first master device and the interconnect in dependence on the looked up memory access permission data.

18. The apparatus according to claim 17, wherein the filtering circuitry is configured to map the target address to the translated address using a translation scheme providing a one-to-one mapping between any given target address and the corresponding translated address.

19. The apparatus according to claim 1, comprising;

said first master device comprising said first cache;

said second master device comprising a second cache; and

said interconnect to manage coherency between said first cache and said at least one other cache or the second master device using coherency protocol transactions exchanged between the first master device and the interconnect;

the second master device comprises a memory permission unit to check, before accessing the second cache, whether a data access operation issued by the second master device is allowed to proceed or triggers a memory access violation, and to perform a lookup in the second cache when the memory permission unit determines that the data access operation issued by the second master device is allowed to proceed; and

the first master device does not have said memory permission unit.

20. The apparatus according to claim 19, wherein in response to a snoop transaction received from the interconnect specifying a target address for which data is currently stored in the first cache in a non-shareable coherency state, the first master device is configured to return a miss indication indicating that the target address missed in said first cache.

21. The apparatus according to claim 19, wherein the first master device has a predetermined coherency mode in which selected coherency transactions are prohibited, said selected coherency transactions including at least coherency transactions capable of causing data to be allocated to the first cache in a shareable state in which coherency is to be maintained between the shareable data and data at said at least one other cache or the second master device;

wherein the first master device is configured to switch to said predetermined coherency mode when processing protected data to be protected from access by at least one other master.

22. The apparatus according to claim 19, wherein the first master device has a predetermined coherency mode in which the first master device ignores incoming snoop transactions and returns a miss indication to the interconnect for said incoming snoop transactions;

wherein the first master device is configured to switch to said predetermined coherency mode when processing protected data to be protected from access by at least one other master.

23. The apparatus according to claim 21, wherein the memory access permission data supports defining a given region of the address space as a read only region for which the first master device is allowed to read data from the given region and is prohibited from writing data to the given region.

24. The apparatus according to claim 20, wherein the filter is configured to permit incoming snoop transactions received from the interconnect to be passed to the first master device independent of the memory access permission data.

25. A data processing method comprising:

intercepting coherency protocol transactions exchanged between a first master device and an interconnect for managing coherency between a first cache comprised by said first master device and at least one other cache or a second master device; and

filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the first master device is allowed to access;

wherein the filtering comprises blocking an outgoing coherency protocol transaction issued from said first master device to said interconnect, when a memory access permission violation is detected for the outgoing coherency protocol transaction in dependence on the memory access permission data;

wherein said memory access permission violation is detected when the outgoing coherency protocol transaction is a read transaction capable of causing data to be stored in said first cache in a shareable modifiable coherency state in which coherency is to be maintained between the data in said first cache and said at least one other cache or the second master device, and the first master device is allowed to modify the data without issuing a further coherency protocol transaction to said interconnect, and the memory access permission data specifies that the first master device is;

prohibited from writing data to a region of the address space including a target address specified by the outgoing coherency protocol transaction; and

permitted to read data from said region of the address space including the target address specified by the outgoing coherency protocol transaction.