Neural network system

• US 10,664,746 B2
• Filed: 10/29/2018
• Issued: 05/26/2020
• Est. Priority Date: 07/17/2018
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lue, Hang-Ting
• Primary Examiner(s): Yang, Han
• Application Number:
  US16/172,921
• Publication Number:
  US 20200026990A1
• Time in Patent Office: 575 Days
• CPC Class Codes: G06F 2207/4824 Neural networks
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A neural network system for execution of a sum-of-products operation includes a memory device and a controller. The memory device includes a 3D array having a plurality of memory cells with programmable conductances disposed in cross-points of a plurality of cell body lines and gate lines, a gate driver coupled to the gate lines and applying control gate voltages in combination with the programmable conductances for corresponding to weights of terms in the sum-of-products operation, a input driver used to apply voltages to the memory cells corresponding to input variables, a plurality of input lines connecting the cell body lines to the input driver, a sensing circuit used to sense currents passing through the memory cells corresponding the terms in the sum-of-products operation, a buffer circuit used to store the terms. The controller is used to control the memory device summing up the terms in the sum-of-products operation.

Claims

1. A neural network (NN) system;

available for execution of a sum-of-products operation comprising;

a memory device comprising;

a three-dimensional (3D) array of cells, having a plurality of memory cells disposed in cross-points of a plurality of cell body lines and a plurality of gate lines, wherein the memory cells have programmable conductances;

a gate driver, coupled to the gate lines and used to apply control gate voltages which are in combination with the programmable conductances of the cells for corresponding to weights of terms in the sum-of-products operation;

an input driver, used to apply voltages to the memory cells corresponding to input variables;

a plurality of input lines, each connecting one of the cell body lines to the input driver for inputting one of the input variables;

a sensing circuit, coupled to the input lines and used to sense a current passing through one of the memory cells corresponding to a corresponding term of the terms in the sum-of-products operation; and

a buffer circuit, coupled to the sensing circuit and used to store the corresponding term; and

a controller, coupled to the memory device and used to control the memory device summing up the terms in the sum-of-products operation.

2. The NN system of claim 1, wherein while the terms in the sum-of-products operation are acquired by the sensing circuits, the terms in the sum-of-products are inputted into the memory device through a plurality of the same input lines corresponding to the cell body lines serving as a second input variables to execute another sum-of-products operation.

3. The NN system of claim 1, wherein the terms in the sum-of-products are sum up in the sensing circuit or in the buffer circuit.

4. The NN system of claim 3, wherein the circuits passing through the memory cells terms are sum up to form a sum of currents corresponding to the sum-of-products.

5. The NN system of claim 1, wherein the memory device further comprises a plurality of output lines each of which connects one of the cell body lines to the sensing circuit.

6. The NN system of claim 1, wherein the memory device comprises a plurality of sensing circuits and a plurality of buffer circuits, each of the sensing circuits is connected to one of the cell body lines for sensing the corresponding term, and each of the buffer circuits is connected to one of the sensing circuit for storing the corresponding term.

7. The NN system of claim 1, further comprising a logic circuit coupled to the memory device and used to sum up a plurality of the corresponding terms respectively stored in the buffer circuits in response to a command directed from the controller.

8. The NN system of claim 1, wherein the buffer circuit comprises at least one of a latch circuit, a static random-access memory (SRAM) and the combination thereof.