Semiconductor device and system using the same

• US 10,664,748 B2
• Filed: 03/06/2017
• Issued: 05/26/2020
• Est. Priority Date: 03/18/2016
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US15/450,315
• Publication Number:
  US 20170270405A1
• Time in Patent Office: 1,177 Days
• Field of Search: 36518909
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal. By subtracting the third current from a differential current between the fourth current and the fifth current, a current that depends on the sum of products of the first analog data and the second analog data is obtained.

Claims

1. A semiconductor device comprising:

a memory cell array; and

an offset circuit,

wherein the memory cell array comprises a first memory cell and a second memory cell,

wherein the offset circuit comprises a first constant current circuit, a second constant current circuit, first to third transistors, a first capacitor, a first wiring, a second wiring, a first output terminal, a second output terminal, and a current mirror circuit,

wherein the first constant current circuit is electrically connected to the first wiring,

wherein the first constant current circuit is configured to supply a first current to the first wiring,

wherein a first terminal of the first transistor is electrically connected to a first terminal of the second transistor,

wherein a gate of the first transistor is electrically connected to a second terminal of the second transistor,

wherein the first terminal of the second transistor is electrically connected to the first wiring,

wherein a first terminal of the third transistor is electrically connected to the second terminal of the second transistor,

wherein a first terminal of the first capacitor is electrically connected to the gate of the first transistor,

wherein the first wiring is electrically connected to the first output terminal,

wherein the second constant current circuit is electrically connected to the second wiring,

wherein the second constant current circuit is configured to supply a second current to the second wiring,

wherein the second wiring is electrically connected to the second output terminal,

wherein the current mirror circuit is configured to output a third current corresponding to a potential of the second wiring from the first wiring and the second wiring,

wherein the first memory cell is electrically connected to the first output terminal, and

wherein the second memory cell is electrically connected to the second output terminal.

2. The semiconductor device according to claim 1,

wherein the first constant current circuit comprises a fourth transistor,

wherein the second constant current circuit comprises a fifth transistor,

wherein the fourth transistor and the fifth transistor each comprise a back gate,

wherein a first terminal of the fourth transistor is electrically connected to the first wiring,

wherein a gate of the fourth transistor is electrically connected to the first terminal of the fourth transistor,

wherein a first terminal of the fifth transistor is electrically connected to the second wiring, and

wherein a gate of the fifth transistor is electrically connected to the first terminal of the fifth transistor.

3. The semiconductor device according to claim 1,

wherein the current mirror circuit comprises a sixth transistor and a seventh transistor,

wherein a first terminal of the sixth transistor is electrically connected to the first wiring,

wherein a gate of the sixth transistor is electrically connected to the second wiring,

wherein a first terminal of the seventh transistor is electrically connected to the second wiring, and

wherein a gate of the seventh transistor is electrically connected to the second wiring.

4. The semiconductor device according to claim 1,

wherein the first memory cell comprises an eighth transistor, a ninth transistor, and a second capacitor,

wherein the second memory cell comprises a tenth transistor, an eleventh transistor, and a third capacitor,

wherein a first terminal of the eighth transistor is electrically connected to a gate of the ninth transistor,

wherein a first terminal of the second capacitor is electrically connected to the first terminal of the eighth transistor,

wherein a first terminal of the ninth transistor is electrically connected to the first output terminal,

wherein a first terminal of the tenth transistor is electrically connected to a gate of the eleventh transistor,

wherein a first terminal of the third capacitor is electrically connected to the first terminal of the tenth transistor, and

wherein a first terminal of the eleventh transistor is electrically connected to the second output terminal.

5. The semiconductor device according to claim 4, wherein the first to eleventh transistors each have a same polarity.

6. The semiconductor device according to claim 4,

wherein at least one of channel formation regions in the first to eleventh transistors comprises an oxide containing at least one of indium, an element M, and zinc, and

wherein the element M is any one of aluminum, gallium, yttrium, and tin.

7. A semiconductor wafer comprising:

a plurality of the semiconductor devices according to claim 1; and

a region for dicing.

8. An electronic device comprising:

the semiconductor device according to claim 1; and

a housing.

9. An electronic device comprising:

the semiconductor device according to claim 1 and is configured to perform processing such as pattern recognition and associative storage.

10. A biometric authentication system comprising:

an electronic device comprising a semiconductor device and is configured to perform processing such as pattern recognition and associative storage; and

a device configured to obtain biological information,

wherein the semiconductor device comprises a memory cell array and an offset circuit,

wherein the memory cell array comprises a first memory cell and a second memory cell,

wherein the offset circuit comprises a first constant current circuit, a second constant current circuit, first to third transistors, a first capacitor, a first wiring, a second wiring, a first output terminal, a second output terminal, and a current mirror circuit,

wherein the first constant current circuit is electrically connected to the first wiring,

wherein the first constant current circuit is configured to supply a first current to the first wiring,

wherein a first terminal of the first transistor is electrically connected to a first terminal of the second transistor,

wherein a gate of the first transistor is electrically connected to a second terminal of the second transistor,

wherein the first terminal of the second transistor is electrically connected to the first wiring,

wherein a first terminal of the third transistor is electrically connected to the second terminal of the second transistor,

wherein a first terminal of the first capacitor is electrically connected to the gate of the first transistor,

wherein the first wiring is electrically connected to the first output terminal,

wherein the second constant current circuit is electrically connected to the second wiring,

wherein the second constant current circuit is configured to supply a second current to the second wiring,

wherein the second wiring is electrically connected to the second output terminal,

wherein the current mirror circuit is configured to output a third current corresponding to a potential of the second wiring from the first wiring and the second wiring,

wherein the first memory cell is electrically connected to the first output terminal, and

wherein the second memory cell is electrically connected to the second output terminal.

11. The biometric authentication system according to claim 10,

wherein the first constant current circuit comprises a fourth transistor,

wherein the second constant current circuit comprises a fifth transistor,

wherein the fourth transistor and the fifth transistor each comprise a back gate,

wherein a first terminal of the fourth transistor is electrically connected to the first wiring,

wherein a gate of the fourth transistor is electrically connected to the first terminal of the fourth transistor,

wherein a first terminal of the fifth transistor is electrically connected to the second wiring, and

wherein a gate of the fifth transistor is electrically connected to the first terminal of the fifth transistor.

12. The biometric authentication system according to claim 10,

wherein the current mirror circuit comprises a sixth transistor and a seventh transistor,

wherein a first terminal of the sixth transistor is electrically connected to the first wiring,

wherein a gate of the sixth transistor is electrically connected to the second wiring,

wherein a first terminal of the seventh transistor is electrically connected to the second wiring, and

wherein a gate of the seventh transistor is electrically connected to the second wiring.

13. The biometric authentication system according to claim 10,

wherein the first memory cell comprises an eighth transistor, a ninth transistor, and a second capacitor,

wherein the second memory cell comprises a tenth transistor, an eleventh transistor, and a third capacitor,

wherein a first terminal of the eighth transistor is electrically connected to a gate of the ninth transistor,

wherein a first terminal of the second capacitor is electrically connected to the first terminal of the eighth transistor,

wherein a first terminal of the ninth transistor is electrically connected to the first output terminal,

wherein a first terminal of the tenth transistor is electrically connected to a gate of the eleventh transistor,

wherein a first terminal of the third capacitor is electrically connected to the first terminal of the tenth transistor, and

wherein a first terminal of the eleventh transistor is electrically connected to the second output terminal.

14. The biometric authentication system according to claim 13, wherein the first to eleventh transistors each have a same polarity.

15. The biometric authentication system according to claim 13,

wherein at least one of channel formation regions in the first to eleventh transistors comprises an oxide containing at least one of indium, an element M, and zinc, and

wherein the element M is any one of aluminum, gallium, yttrium, and tin.

16. A video distribution system comprising:

an electronic device comprising a semiconductor device and is configured to perform processing such as pattern recognition and associative storage,

wherein the video distribution system is configured to encode a video data, and

wherein the video distribution system is configured to send an encoded video data,

wherein the semiconductor device comprises a memory cell array and an offset circuit,

wherein the memory cell array comprises a first memory cell and a second memory cell,

wherein the offset circuit comprises a first constant current circuit, a second constant current circuit, first to third transistors, a first capacitor, a first wiring, a second wiring, a first output terminal, a second output terminal, and a current mirror circuit,

wherein the first constant current circuit is electrically connected to the first wiring,

wherein the first constant current circuit is configured to supply a first current to the first wiring,

wherein a first terminal of the first transistor is electrically connected to a first terminal of the second transistor,

wherein a gate of the first transistor is electrically connected to a second terminal of the second transistor,

wherein the first terminal of the second transistor is electrically connected to the first wiring,

wherein a first terminal of the third transistor is electrically connected to the second terminal of the second transistor,

wherein a first terminal of the first capacitor is electrically connected to the gate of the first transistor,

wherein the first wiring is electrically connected to the first output terminal,

wherein the second constant current circuit is electrically connected to the second wiring,

wherein the second constant current circuit is configured to supply a second current to the second wiring,

wherein the second wiring is electrically connected to the second output terminal,

wherein the current mirror circuit is configured to output a third current corresponding to a potential of the second wiring from the first wiring and the second wiring,

wherein the first memory cell is electrically connected to the first output terminal, and

wherein the second memory cell is electrically connected to the second output terminal.