Gate driver and display panel using the same

• US 10,665,172 B2
• Filed: 06/09/2017
• Issued: 05/26/2020
• Est. Priority Date: 11/21/2016
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Lee, Jung Min, Kim, Jin Hwan, Kim, Woo Chan
• Primary Examiner(s): Sitta, Grant
• Application Number:
  US15/618,387
• Publication Number:
  US 20180144688A1
• Time in Patent Office: 1,082 Days
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2310/0213 controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
• CPC Class Codes: G09G 2310/0218 with collection of electrodes in groups for n-dimensional addressing
• CPC Class Codes: G09G 2310/0221 with use of split matrices G09G3/3644 and G09G3/3666 take precedence
• CPC Class Codes: G09G 2310/0232 Special driving of display border areas
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/04 Partial updating of the display screen
• CPC Class Codes: G09G 2310/062 Waveforms for resetting a plurality of scan lines at a time
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/023 using energy recovery or conservation
• CPC Class Codes: G09G 2354/00 Aspects of interface with display user
• CPC Class Codes: G09G 3/003 to produce spatial visual effects
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A display panel includes a first plurality of pixels in first pixel rows corresponding to a first plurality of gate lines, a second plurality of pixels in second pixel rows corresponding to a second plurality of gate lines, and a gate driver coupled to the first plurality of gate lines and the second plurality of gate lines, the gate driver is configured to in a first display mode, turn on the first plurality of pixels and the second plurality of pixels, and in a second display mode, turn off the first plurality of pixels and turn on the second plurality of pixels. By turning off the pixels in the plurality of rows disposed in the dark areas, the number of the pixels to be driven can be reduced while obtaining a sufficient pixel compensation time, thereby driving the display panel at high speed.

Claims

1. A display panel having a display area and a non-display area surrounding the display area comprising:

a first plurality of pixels in first pixel rows disposed along a first edge of the display panel, the first pixel rows corresponding to a first plurality of gate lines;

a second plurality of pixels in second pixel rows corresponding to a second plurality of gate lines;

a third plurality of pixels in third pixel rows disposed along a second edge of the display panel that is opposite to the first edge, the third pixel rows corresponding to a third plurality of gate lines, wherein the second plurality of pixels are between the first plurality of pixels and the third plurality of pixels; and

a gate driver coupled to the first plurality of gate lines, the second plurality of gate lines, and the third plurality of gate lines, the gate driver configured to;

in a first display mode that displays an image, turn on the first plurality of pixels, the second plurality of pixels, and the third plurality of pixels; and

in a second display mode that displays the image in virtual reality, turn off the first plurality of pixels and the third plurality of pixels, and turn on the second plurality of pixels such that all of the second plurality of pixels are capable of being used for displaying the image,

wherein the gate driver comprises;

a plurality of cascaded driver stages that include a first plurality of cascaded driver stages to drive at least the first plurality of gate lines and a second plurality of cascaded driver stages to drive at least the second plurality of gate lines, and

a first cut off transistor to selectively block an output signal of a driver stage of the first plurality of cascaded driver stages from reaching an input of an initial driver stage of the second plurality of cascaded driver stages in the second display mode,

wherein each of the first edge and the second edge is a periphery area of the display area adjacent to the non-display area, and

wherein during the second display mode that displays the image in virtual reality, the display panel is fixed at a location in front of a user'"'"'s eyes using a structure,

wherein at least one driver stage of the first plurality of cascaded driver stages comprises;

a first output transistor and a second output transistor that are alternately turned on, the first output transistor connected to a gate high voltage line and the second output transistor connected to a gate low voltage line or a clock line; and

a first auxiliary transistor having a gate connected to an enable line, an electrode connected to the gate low voltage line or the clock line, and another electrode connected to a gate of the first output transistor.

2. The display panel of claim 1, wherein:

in the first display mode, the gate driver sequentially drives a gate signal to the first plurality of gate lines, the second plurality of gate lines, and the third plurality of gate lines; and

in the second display mode, the gate driver sequentially drives a gate signal to the second plurality of gate lines, and applies a DC voltage to the first plurality of gate lines and the third plurality of gate lines.

3. The display panel of claim 1, wherein in the first display mode, the first cut off transistor passes the output signal of a last driver stage of the first plurality of cascaded driver stages to the input of the initial driver stage of the second plurality of cascaded driver stages.

4. The display panel of claim 1, wherein the plurality of cascaded driver stages further comprises a third plurality of cascaded driver stages to drive at least the third plurality of gate lines,

wherein the gate driver further comprises a second cut off transistor to selectively block an output signal of a last driver stage of the second plurality of cascaded driver stages from reaching an input of an initial driver stage of the third plurality of cascaded driver stages during the second display mode.

5. The display panel of claim 1, further comprising:

a start pulse voltage line to carry a start pulse voltage; and

a first control transistor to selectively control whether the start pulse voltage is provided from the start pulse voltage line to an initial driver stage of the first plurality of cascaded driver stages.

6. The display panel of claim 5, further comprising:

a second control transistor to selectively control whether the start pulse voltage is provided from the start pulse voltage line to the initial driver stage of the second plurality of cascaded driver stages.

7. The display panel of claim 1, wherein the at least one driver stage of the first plurality of cascaded driver stages comprises:

a second auxiliary transistor having a gate connected to the enable line, an electrode connected to a gate of the second output transistor, and another electrode connected to the gate high voltage line.

8. The display panel of claim 1,

wherein the first output transistor comprises a plurality of serially connected transistors having connected gate electrodes.

9. The display panel of claim 1, wherein the gate lines are scan lines or emission lines.

10. The display panel of claim 1, wherein in the second display mode, the gate driver turns on the second plurality of pixels and respectively drives a voltage to the first plurality of pixels and the third plurality of pixels via the first gate lines and the third gate lines that maintain the first plurality of pixels and the third plurality of pixels off throughout each corresponding frame period.

11. The display panel of claim 1, wherein in the second display mode, the first pixel rows and the third pixel rows are in a dark area of the display panel that are along the first edge and the second edge of the display panel outside of a human viewing angle range.

12. The display panel of claim 1, wherein the first edge of the display panel and the second edge of the display panel are shorter than a third edge and a fourth edge of the display panel that are perpendicular to the first edge and the second edge.

13. The display panel of claim 1, wherein a frame period in the second display mode is shorter than a frame period of the first display mode.

14. A display panel having a display area and a non-display area surrounding the display area comprising:

a first plurality of pixels in first pixel rows disposed along a first edge of the display panel, the first pixel rows corresponding to a first plurality of gate lines;

a second plurality of pixels in second pixel rows corresponding to a second plurality of gate lines;

a third plurality of pixels in third pixel rows disposed along a second edge of the display panel that is opposite to the first edge, the third pixel rows corresponding to a third plurality of gate lines, wherein the second plurality of pixels are between the first plurality of pixels and the third plurality of pixels; and

a gate driver coupled to the first plurality of gate lines, the second plurality of gate lines, and the third plurality of gate lines, the gate driver configured to;

in a first display mode that displays an image, turn on the first plurality of pixels, the second plurality of pixels, and the third plurality of pixels; and

in a second display mode that displays the image in virtual reality, turn off the first plurality of pixels and the third plurality of pixels, and turn on the second plurality of pixels such that all of the second plurality of pixels are capable of being used for displaying the image,

wherein the gate driver comprises;

a plurality of cascaded driver stages that include a first plurality of cascaded driver stages to drive at least the first plurality of gate lines and a second plurality of cascaded driver stages to drive at least the second plurality of gate lines; and

a first cut off transistor to selectively block an output signal of a last driver stage of the first plurality of cascaded driver stages from reaching an input of an initial driver stage of the second plurality of cascaded driver stages in the second display mode,

wherein each of the first edge and the second edge is a periphery area of the display area adjacent to the non-display area, and

wherein during the second display mode that displays the image in virtual reality, the display panel is fixed at a location in front of a user'"'"'s eyes using a structure,

wherein at least one driver stage of the first plurality of cascaded driver stages comprises;

a circuit block causing an output of the driver stage to be same as an input to the circuit block; and

an auxiliary transistor having a gate connected to an enable line, an electrode connected to a gate high voltage line, and another electrode connected to the input of the circuit block.