Memory device and operating method thereof

• US 10,665,291 B2
• Filed: 11/13/2018
• Issued: 05/26/2020
• Est. Priority Date: 04/19/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Lee, Hee Youl
• Primary Examiner(s): Hidalgo, Fernando
• Application Number:
  US16/189,702
• Publication Number:
  US 20190325938A1
• Time in Patent Office: 560 Days
• Field of Search: 36518523
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H03K 19/1776 for memories

Abstract

A memory device includes: a memory cell array including a plurality of memory cells respectively coupled to a plurality of word lines; a peripheral circuit configured to perform at least one program loop including applying a program voltage to selected memory cells coupled to a selected word line among the plurality of word lines and determining whether the selected memory cells have been completely programmed; and control logic configured to control the peripheral circuit to, while the program voltage is being applied to the selected word line, apply program control voltages of different levels to bit lines respectively coupled to memory cells in a first memory cell group among the selected memory cells and apply a program allowable voltage to bit lines respectively coupled to memory cells in a second memory cell group among the selected memory cells.

Claims

1. A memory device comprising:

a memory cell array including a plurality of memory cells respectively coupled to a plurality of word lines;

a peripheral circuit configured to perform at least one program loop including applying a program voltage to selected memory cells coupled to a selected word line among the plurality of word lines and determining whether the selected memory cells have been completely programmed; and

control logic configured to control the peripheral circuit to, while the program voltage is being applied to the selected word line, apply program control voltages of different levels, which are set according to target program states, to bit lines respectively coupled to memory cells in a first memory cell group among the selected memory cells and apply a program allowable voltage, which is set at a same level regardless of the target program states, to bit lines respectively coupled to memory cells in a second memory cell group among the selected memory cells.

2. The memory device of claim 1, wherein the selected memory cells have, as a target program state, any one program state among first to nth program states (n is a natural number greater than 1),

wherein the program voltage corresponds to the highest program state among target program states of the memory cells in the first memory cell group.

3. The memory device of claim 1, wherein the control logic controls the peripheral circuit to apply a program inhibit voltage to a bit line coupled to a memory cell determined to have been completely programmed among the selected memory cells.

4. The memory device of claim 1, wherein the memory cells in the first memory cell group have, as a target program state, any one program state among first to kth program states (k is a natural number greater than 1), and

the memory cells in the second memory cell group have, as a target program state, any one program state among (k+1)th to nth program states (n is a natural number greater than (k+1)).

5. The memory device of claim 1, wherein the memory cells in the first memory cell group have, as a target program state, any one program state among pth to qth program states (p is a natural number that is greater than 1 and less than q, and q is a natural number greater than p), and

the memory cells in the second memory cell group have, as a target program state, a program state, except the pth to qth program states, among the first to nth program states (n is a natural number greater than q).

6. The memory device of claim 1, wherein the program voltage is increased by a step voltage whenever the at least one program loop is repeated.

7. The memory device of claim 6, wherein the program control voltage has a high level when the target program state of the memory cells in the first memory cell group is low.

8. The memory device of claim 1, wherein the program control voltages are applied in a first program loop of the at least one program loop while the program voltage is being applied.

9. The memory device of claim 8, wherein, whenever the at least one program loop is repeated, the program voltage is increased by a step voltage.

10. The memory device of claim 8, wherein the control logic controls the peripheral circuit to apply a program inhibit voltage to a bit line coupled to a memory cell determined to have been completely programmed among the memory cells in the first memory cell group.

11. A method for operating a memory device including a plurality of memory cells respectively coupled to a plurality of word lines, the method comprising:

performing at least one program loop including applying a program voltage to selected memory cells coupled to a selected word line among the plurality of word lines and determining whether the selected memory cells have been completely programmed; and

while the program voltage is being applied to the selected word line, applying program control voltages of different levels to bit lines respectively coupled to memory cells in a first memory cell group among the selected memory cells and applying a program allowable voltage to bit lines respectively coupled to memory cells in a second memory cell group among the selected memory cells,

wherein the levels of program control voltages are set according to target program states and the program allowable voltage is set at a same level regardless of the target program states.

12. The method of claim 11, wherein, in the applying of the program voltage, a voltage corresponding to the highest program state among first to nth program states (n is a natural number greater than 1) is applied.

13. The method of claim 11, wherein the applying of the program control voltages comprises applying a program inhibit voltage to a bit line coupled to a memory cell determined to have been completely programmed among the selected memory cells.

14. The method of claim 11, wherein the performing of the at least one program loop includes:

applying a program control voltage such that the memory cells in the first memory cell group have, as a target program state, any one program state among first to kth program states (k is a natural number greater than

     1); and

applying a program allowable voltage such that the memory cells in the second memory cell group have, as a target program state, any one program state among (k+1)th to nth program states (n is a natural number greater than (k+1)).

15. The method of claim 11, wherein the performing of the at least one program loop includes:

applying a program control voltage such that the memory cells in the first memory cell group have, as a target program state, any one program state among pth to qth program states (p is a natural number that is greater than 1 and less than q, and q is a natural number greater than p); and

applying a program allowable voltage such that the memory cells included in the second memory cell group have, as a target program state, a program state, except the pth to qth program states, among the first to nth program states (n is a natural number greater than q).

16. The method of claim 11, wherein, in the applying of the program voltage, the program voltage is increased by a step voltage whenever the at least one program loop is repeated.

17. The method of claim 16, wherein the applying of the program control voltages comprises applying a high voltage level when the target program state of the memory cells in the first memory cell group is low.

18. The method of claim 11, wherein the performing of the at least one program loop includes applying the program control voltages in a first program loop of the at least one program loop while the program voltage is being applied.

19. The method of claim 18, wherein, in the applying of the program voltage, the program voltage is increased by a step voltage whenever the at least one program loop is repeated, and

the applying of the program allowable voltage comprises applying a program inhibit voltage to a bit line coupled to a memory cell determined to have been completely programmed.