Host device connectable to memory device performing patrol read and memory device performing patrol read

• US 10,665,305 B2
• Filed: 03/07/2016
• Issued: 05/26/2020
• Est. Priority Date: 09/09/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Yao, Hiroshi, Suzuki, Riki, Hida, Toshikatsu
• Primary Examiner(s): Truong, Loan L. T.
• Application Number:
  US15/062,637
• Publication Number:
  US 20170069395A1
• Time in Patent Office: 1,541 Days
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

According to one embodiment, a controller of a host causes a memory device to transit from a first state that is an active state to a second state that is a sleep state in a case where there is no access to the memory device for a first time or more. The controller causes the memory device to transit from the second state to the first state in a case where there is no access to the memory device for a second time or more after the transition to the second state.

Claims

1. A memory device connectable to a host device, the memory device comprising:

a nonvolatile memory including a plurality of blocks; and

a controller configured to;

execute patrol read, the patrol read including reading first data, testing the read first data, and refreshing data stored inside a block including second data that is not successful in the test among the read first data, the first data being data of a certain unit stored in the nonvolatile memory, the testing including checking whether the read first data includes a bit error and counting a number of error bits of the read first data, the second data that is not successful in the test being data of which the number of error bits exceeds a certain threshold in the test, the refreshing selecting from a first refreshing or a second refreshing that is different from the first refreshing; and

notify refreshing to be executed among the first refreshing and the second refreshing to the host device.

2. The memory device according to claim 1, wherein the controller notifies information representing necessity/no-necessary of the patrol read to the host device.

3. The memory device according to claim 1, wherein the controller notifies start and end of the patrol read, and wherein,

when the controller notifies the start of the patrol read to the host device, the controller notifies a scheduled end time of the patrol read to the host device.

4. The memory device according to claim 1, wherein the controller calculates an interval time from end of the patrol read to next startup of the patrol read and notifies information representing the calculated interval time to the host device.

5. The memory device according to claim 1, wherein the controller selects a ratio of a target area of the test to an area of the nonvolatile memory and notifies information representing the selected ratio to the host device.

6. The memory device according to claim 1,

wherein the block includes a plurality of memory cells, and

wherein the controller

executes the first refreshing in a case where the number of error bits of a first block is more than a first threshold and less than a second threshold, the first refreshing including reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block, the second threshold being larger than the first threshold,

executes the second refreshing in a case where the number of error bits of the first block is more than the second threshold, the second refreshing including moving data of the first block to a second block excluding the first block.

7. A memory device connectable to a host device, the memory device comprising:

a nonvolatile memory including a plurality of blocks; and

a controller configured to;

execute patrol read, the patrol read including reading first data, testing the read first data, and refreshing data stored inside a block including second data that is not successful in the test among the read first data, the first data being data of a certain unit stored in the nonvolatile memory, the testing including checking whether the read first data includes a bit error and counting a number of error bits of the read first data, the second data that is not successful in the test being data of which the number of error bits exceeds a certain threshold in the test, the refreshing selecting from a first refreshing, a second refreshing or a third refreshing, the second refreshing being different from the first refreshing, the third refreshing being different from the second refreshing and the first refreshing; and

notify, to the host device, refreshing to be executed among the first refreshing, the second refreshing, and the third refreshing.

8. The memory device according to claim 7,

wherein the block includes a plurality of memory cells, and

wherein the controller

executes the first refreshing in a case where the number of error bits of a first block is more than a first threshold and less than a second threshold, the first refreshing including reprogramming a plurality of second memory cells among a plurality of first memory cells included in the first block, the second threshold being larger than the first threshold,

executes the second refreshing in a case where the number of error bits of the first block is more than the second threshold and less than a third threshold, the third threshold being larger than the second threshold, the second refreshing including reading data of the first block, erasing the first block, and writing the read data into the erased first block,

executes the third refreshing in a case where the number of error bits of the first block is more than a third threshold, the third refreshing including moving data of the first block to a second block excluding the first block.