Source/drain performance through conformal solid state doping

• US 10,665,452 B2
• Filed: 06/26/2018
• Issued: 05/26/2020
• Est. Priority Date: 05/02/2016
• Status: Active Grant

• Current Assignee: ASM IP Holdings B.V.
• Original Assignee: ASM IP Holdings B.V.
• Inventors: Xie, Qi, de Roest, David, Woodruff, Jacob, Givens, Michael Eugene, Maes, Jan Willem, Blanquart, Timothee
• Primary Examiner(s): Ahmad, Khaja
• Application Number:
  US16/018,692
• Publication Number:
  US 20180308686A1
• Time in Patent Office: 700 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/2254 from or through or into an applied layer, e.g. photoresist, nitrides
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843

Abstract

A method for improving source/drain performance through conformal solid state doping and its resulting device are disclosed. Specifically, the doping takes place through an atomic layer deposition of a dopant layer. Embodiments of the invention may allow for an increased doping layer, improved conformality, and reduced defect formation, in comparison to alternate doping methods, such as ion implantation or epitaxial doping.

Claims

1. A method of forming a semiconductor device for source/drain applications comprising:

providing a substrate for processing in a reaction chamber, the substrate having a surface and at least one formed source/drain region;

performing an atomic layer deposition of a dopant layer on the substrate surface for incorporation of dopant into the at least one formed source/drain region; and

performing an atomic layer deposition of a capping layer on the dopant layer;

wherein, after the atomic layer deposition of the capping layer, the semiconductor device is subject to a drive-in anneal step to diffuse dopant from the dopant layer into at least one of the formed source/drain regions, producing a doping level near an interface of greater than 1×

10²⁰/cm³ with a diffusion depth less than 30 nm, and

wherein performing the atomic layer deposition of the dopant layer on the substrate surface for incorporation of dopant into the at least one formed source/drain region comprises;

pulsing a first precursor onto the substrate, wherein the first precursor is at least one of;

SbCl₃, SbF₃, SbI₃, and SbBr₃;

purging the first precursor from the reaction chamber with a purge gas, wherein the purge gas comprises at least one of;

N₂, Ar, or an inert gas;

pulsing a second precursor onto the substrate, wherein the second precursor is at least one of;

trimethyl silyl antimony or triethyl silyl antimony; and

purging the second precursor from the reaction chamber with the purge gas.

2. The method of claim 1, further comprising:

removing the capping layer.

3. The method of claim 1, wherein the substrate comprises at least one of:

silicon, germanium, silicon germanium, or a III-V material.

4. The method of claim 1, wherein the dopant layer comprises at least one of:

antimony, boron, arsenic, phosphorus, magnesium, carbon, silicon, or sulfur.

5. The method of claim 1, wherein the capping layer comprises at least one of:

silicon dioxide (SiO₂), titanium nitride (TiN), silicon nitride (SiN), aluminum nitride (AlN), silicon-containing carbon, or aluminum oxide (Al₂O₃).

6. The method of claim 1, wherein the drive-in anneal is performed at a temperature greater than 400°

C.

7. The method of claim 1, wherein the atomic layer deposition of the dopant layer forms a channel material for an NMOS device.

8. The method of claim 1, wherein the substrate comprises germanium.

18. The method of claim 1, the method producing a doping level near an interface of approximately 5×

10²⁰/cm³.

9. A method of forming a semiconductor device for source/drain applications comprising:

providing a substrate for processing in a reaction chamber, the substrate having a surface and a formed source/drain;

performing an atomic layer deposition of a dopant layer on the substrate surface for incorporation of dopant into the at least one formed source/drain region, producing a doping level near an interface of greater than 1×

10²⁰/cm³ with a diffusion depth less than 30 nm; and

performing an atomic layer deposition of a capping layer on the dopant layer,

wherein performing the atomic layer deposition of the dopant layer on the substrate surface for incorporation of dopant into the at least one formed source/drain region comprises;

pulsing a first precursor onto the substrate, wherein the first precursor is at least one of;

SbCl₃, SbF₃, SbI₃, and SbBr₃;

purging the first precursor from the reaction chamber with a purge gas, wherein the purge gas comprises at least one of;

N₂, Ar, or an inert gas;

pulsing a second precursor onto the substrate, wherein the second precursor is at least one of;

trimethyl silyl antimony or triethyl silyl antimony; and

purging the second precursor from the reaction chamber with the purge gas.

10. The method of claim 9, wherein the substrate comprises at least one of:

silicon, germanium, silicon germanium, or a III-V material.

11. The method of claim 9, wherein the dopant layer comprises at least one of:

antimony, boron, arsenic, phosphorus, magnesium, carbon, silicon, or sulfur.

12. The method of claim 9, wherein the capping layer comprises at least one of:

titanium;

titanium nitride (TiN_x);

titanium silicide (TiSi_x);

tantalum silicide (TaSi_x);

or niobium silicide (NbSi_x).

13. The method of claim 9, wherein a drive-in anneal is performed on the substrate at a temperature greater than 400°

C.

14. The method of claim 9, wherein the atomic layer deposition of the dopant layer forms a channel material for an NMOS device.

15. The method of claim 9, wherein the substrate comprises germanium.

16. The method of claim 9, wherein performing the atomic layer deposition of the capping layer comprises:

pulsing a first precursor onto the substrate, wherein the first precursor is at least one of;

TiCl_x, TaF_x, NbF_x, or a metal halide;

purging the first precursor from the reaction chamber with a purge gas, wherein the purge gas comprises at least one of;

N₂, Ar, or an inert gas;

pulsing a second precursor onto the substrate, wherein the second precursor is at least one of;

ammonia (NH₃) or silane; and

purging the second precursor from the reaction chamber with the purge gas.

17. The method of claim 9, the method producing a doping level near an interface of approximately 5×

10²⁰/cm³.