Three-dimensional semiconductor chip containing memory die bonded to both sides of a support die and methods of making the same

• US 10,665,581 B1
• Filed: 01/23/2019
• Issued: 05/26/2020
• Est. Priority Date: 01/23/2019
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Zhou, Fei, Makala, Raghuveer S., Rajashekhar, Adarsh, Sharangpani, Rahul
• Primary Examiner(s): Lozada, Alfredo Bermudez
• Application Number:
  US16/255,413
• Time in Patent Office: 489 Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08 of an individual bonding area
• CPC Class Codes: H01L 2224/08121 the connected bonding areas being not aligned with respect to each other
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/09181 On opposite sides of the body
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/48477 being a pre-ball (i.e. a ball formed by capillary bonding)
• CPC Class Codes: H01L 2224/48499 Material of the auxiliary connecting means
• CPC Class Codes: H01L 2224/73201 on the same surface
• CPC Class Codes: H01L 2224/73251 on different surfaces
• CPC Class Codes: H01L 2224/80895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/43 : Manufacturing methods
• CPC Class Codes: H01L 24/46 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14511 : EEPROM
• CPC Class Codes: H10B 41/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

A support die includes complementary metal-oxide-semiconductor (CMOS) devices, front support-die bonding pads electrically connected to a first subset of the peripheral circuitry, and backside bonding structures electrically connected to a second subset of the peripheral circuitry. A first memory die including a first three-dimensional array of memory elements is bonded to the support die. First memory-die bonding pads of the first memory die are bonded to the front support-die bonding pads. A second memory die including a second three-dimensional array of memory elements is bonded to the support die. Second memory-die bonding pads of the second memory die are bonded to the backside bonding structures.

Claims

1. A bonded assembly comprising:

a support die comprising a peripheral circuitry, front support-die bonding pads electrically connected to a first subset of the peripheral circuitry, and backside bonding structures electrically connected to a second subset of the peripheral circuitry;

a first memory die comprising a first three-dimensional array of memory elements and first memory-die bonding pads that are bonded to the front support-die bonding pads; and

a second memory die comprising a second three-dimensional array of memory elements and second memory-die bonding pads that are bonded to the backside bonding structures;

wherein the first memory-die bonding pads are bonded to the front support-die bonding pads by metal-to-metal bonding; and

the second memory-die bonding pads are bonded to the backside bonding structures by metal-to-metal bonding.

2. The bonded assembly of claim 1, wherein an electrically conductive path extends through the support die between one of the front support-die bonding pads and one of the backside bonding structures.

3. The bonded assembly of claim 2, wherein the electrically conductive path is connected to a node of one of the peripheral circuitry in the support die.

4. The bonded assembly of claim 1, wherein an intersection set of the first subset of the peripheral circuitry and the second subset of the peripheral circuitry comprises a third subset of the peripheral circuitry that is electrically connected to electrical nodes within the first memory die and to electrical nodes within the second memory die.

5. The bonded assembly of claim 1, wherein the peripheral circuitry comprises a sense amplifier and a first switchable electrical connection circuit, wherein the first switchable electrical connection circuit is configured to connect the sense amplifier to a set of nodes that is selected from:

a set of first bit lines located within the first memory die; and

a set of second bit lines located within the second memory die.

6. The bonded assembly of claim 5, wherein the peripheral circuitry comprises a word line driver and a second switchable electrical connection circuit, wherein the second switchable electrical connection circuit is configured to connect the word line driver to a set of nodes that is selected from:

a set of first word lines located within the first memory die; and

a set of second word lines located within the second memory die.

7. The bonded assembly of claim 1, wherein the peripheral circuitry comprises:

a first bit line driver connected to first bit lines within the first memory die through a first subset of the front support-die bonding pads and a first subset of the first memory-die bonding pads;

a second bit line driver connected to second bit lines within the second memory die through a first subset of the backside bonding structures and a first subset of the second memory-die bonding pads;

a first word line driver connected to first word lines within the first memory die through a second subset of the front support-die bonding pads and a second subset of the first memory-die bonding pads; and

a second word line driver connected to second word lines within the second memory die through a second subset of the backside bonding structures and a second subset of the second memory-die bonding pads.

8. The bonded assembly of claim 1, wherein:

the peripheral circuitry comprises a source power supply circuit configured to drive a first source line in the first memory die and a second source line in the second memory die; and

the support die comprises a source power distribution network including a subset of metal interconnect structures and connected to the source power supply circuit, a subset of the front support-die bonding pads, and a subset of the backside bonding structures.

9. The bonded assembly of claim 1, further comprising:

external bonding pads located on the support die; and

solder structures located on the external bonding pads.

10. The bonded assembly of claim 1, further comprising:

external bonding pads located on at least one of the first memory die and the second memory die; and

solder structures located on the external bonding pads.

11. The bonded assembly of claim 1, wherein one of the backside bonding structures comprises a through-substrate via structure extending through a semiconductor substrate of the support die, laterally electrically insulated from the semiconductor substrate by a tubular insulating spacer, and contacting one of the second memory-die bonding pads.

12. The bonded assembly of claim 1, wherein one of the backside bonding structures comprises:

a through-substrate via structure extending through a semiconductor substrate of the support die and laterally electrically insulated from the semiconductor substrate by a tubular insulating spacer; and

a backside support-die bonding pad contacting the through-substrate via structure and bonded to one of the second memory-die bonding pads.

13. The bonded assembly of claim 1, wherein each of the first memory die and the second memory die comprises:

an alternating stack of insulating layers and electrically conductive layers forming word lines, the alternating stack having stepped surfaces in which a subset of the electrically conductive layers has a lateral extent that increases with a distance from the support die;

memory stack structures vertically extending through the alternating stack and including a respective vertical semiconductor channel and a respective set of vertically stacked memory elements located at levels of the electrically conductive layers; and

word line contact via structures contacting a respective one of the word lines and extending from the respective one of the word lines toward the support die.

14. A bonded assembly comprising:

a support die comprising a peripheral circuitry, front support-die bonding pads electrically connected to a first subset of the peripheral circuitry, and backside bonding structures electrically connected to a second subset of the peripheral circuitry;

a first memory die comprising a first three-dimensional array of memory elements and first memory-die bonding pads that are bonded to the front support-die bonding pads; and

a second memory die comprising a second three-dimensional array of memory elements and second memory-die bonding pads that are bonded to the backside bonding structures;

wherein the peripheral circuitry comprises;

a first bit line driver connected to first bit lines within the first memory die through a first subset of the front support-die bonding pads and a first subset of the first memory-die bonding pads;

a second bit line driver connected to second bit lines within the second memory die through a first subset of the backside bonding structures and a first subset of the second memory-die bonding pads;

a first word line driver connected to first word lines within the first memory die through a second subset of the front support-die bonding pads and a second subset of the first memory-die bonding pads; and

a second word line driver connected to second word lines within the second memory die through a second subset of the backside bonding structures and a second subset of the second memory-die bonding pads.

15. A bonded assembly comprising:

a support die comprising a peripheral circuitry, front support-die bonding pads electrically connected to a first subset of the peripheral circuitry, and backside bonding structures electrically connected to a second subset of the peripheral circuitry;

a first memory die comprising a first three-dimensional array of memory elements and first memory-die bonding pads that are bonded to the front support-die bonding pads; and

a second memory die comprising a second three-dimensional array of memory elements and second memory-die bonding pads that are bonded to the backside bonding structures;

wherein;

the peripheral circuitry comprises a source power supply circuit configured to drive a first source line in the first memory die and a second source line in the second memory die; and

the support die comprises a source power distribution network including a subset of metal interconnect structures and connected to the source power supply circuit, a subset of the front support-die bonding pads, and a subset of the backside bonding structures.