Gate cut with integrated etch stop layer

• US 10,665,589 B2
• Filed: 08/03/2018
• Issued: 05/26/2020
• Est. Priority Date: 09/07/2016
• Status: Active Grant

• Current Assignee: Tessera LLC (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Bergendahl, Marc A., Greene, Andrew M., Venigalla, Rajasekhar
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US16/054,417
• Publication Number:
  US 20180350810A1
• Time in Patent Office: 662 Days
• Field of Search: 257401, 257619
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.

Claims

1. An electrical device comprising:

a first active region having a first gate structure;

a second active region having a second gate structure, wherein the first and second gate structures are aligned to one another and separated by a gate cut trench;

a first portion of a conformal dielectric layer on at least sidewall surfaces of the gate cut trench;

a dielectric fill filling a lower portion of the gate cut trench; and

a power rail in an upper portion of the gate cut trench, wherein a second portion of the conformal dielectric layer separates the dielectric fill from the power rail in which the first and second portions of the conformal dielectric layer are comprised of hafnium oxide.

2. The electrical device of claim 1, wherein the first gate structure is present on a channel region on at least one fin structure in the first active region.

3. The electrical device of claim 2, wherein the at least one fin structure in the first active region is comprised of a type IV semiconductor material.

4. The electrical device of claim 2, wherein the second gate structure is present on at least one fin structure in the second active region.

5. The electrical device of claim 1, wherein the conformal dielectric layer obstructs the power rail from shorting to the first and second gate structure.

6. The electrical device of claim 1, wherein the gate cut trench is overlying an isolation region.

7. The electrical device of claim 6, wherein the isolation region is an oxide containing dielectric.

8. An electrical device comprising:

a first active region having a first gate structure;

a second active region having a second gate structure, wherein the first and second gate structures are aligned to one another and separated by a gate cut trench;

a first portion of a etch stop dielectric layer on at least sidewall surfaces of the gate cut trench; and

a power rail in the gate cut trench, wherein a second portion of the conformal dielectric layer separates the dielectric fill from the power rail in which the first and second portions of the conformal dielectric layer are comprised of hafnium oxide.

9. The electrical device of claim 8, wherein the first gate structure is present on a channel region on at least one fin structure in the first active region.

10. The electrical device of claim 9, wherein the at least one fin structure in the first active region is comprised of a type IV semiconductor material.

11. The electrical device of claim 8, wherein the etch stop layer obstructs the power rail from shorting to the first and second gate structure.

12. The electrical device of claim 8, wherein the power rail fills an entirety of the gate cut trench.

13. The electrical device of claim 8, wherein the gate cut trench is overlying an isolation region.

14. The electrical device of claim 8, wherein the isolation region is an oxide containing dielectric.

15. An electrical device comprising:

a first active region having a first gate structure;

a second active region having a second gate structure, wherein the first and second gate structures are aligned to one another and separated by a gate cut trench, the gate cut trench is overlying an isolation region;

a first portion of a etch stop dielectric layer on at least sidewall surfaces of the gate cut trench; and

a power rail in the gate cut trench, wherein a second portion of the conformal dielectric layer separates the dielectric fill from the power rail in which the first and second portions of the conformal dielectric layer are comprised of hafnium oxide.

16. The electrical device of claim 15, wherein the first gate structure is present on a channel region on at least one fin structure in the first active region.

17. The electrical device of claim 15, wherein the at least one fin structure in the first active region is comprised of a type IV semiconductor material.