Insulative structure with diffusion break integral with isolation layer and methods to form same

• US 10,665,669 B1
• Filed: 02/26/2019
• Issued: 05/26/2020
• Est. Priority Date: 02/26/2019
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Frougier, Julien
• Primary Examiner(s): Menz, Douglas M
• Application Number:
  US16/285,657
• Time in Patent Office: 455 Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An IC structure according to the disclosure includes an insulative structure overlying a substrate and set of STIs. The insulative structure includes an isolation layer contacting an upper surface of the substrate, and a diffusion break region integral with and extending from the isolation layer, wherein the diffusion break region horizontally separates a pair of upper surfaces of the isolation layer. A pair of active semiconductor layers, each positioned on a respective one of the pair of upper surfaces of the isolation layer, are adjacent opposing sidewalls of the diffusion break region. The isolation layer electrically separates the pair of active semiconductor layers from the substrate, and the diffusion break region electrically separates the pair of active semiconductor layers from each other.

Claims

1. An integrated circuit (IC) structure comprising:

a substrate;

a set of shallow trench isolations (STIs) adjacent opposing sidewalls of the substrate;

an insulative structure overlying the substrate, the insulative structure including;

an isolation layer contacting an upper surface of the substrate, and

a diffusion break region integral with and extending from the isolation layer, wherein the diffusion break region horizontally separates a pair of upper surfaces of the isolation layer;

a pair of active semiconductor layers each positioned on a respective one of the pair of upper surfaces of the isolation layer, each active semiconductor layer being adjacent an opposing sidewall of the diffusion break region; and

an inter-level dielectric (ILD) over the set of STIs and adjacent opposing sidewalls of the insulative structure;

wherein the isolation layer electrically separates the pair of active semiconductor layers from the substrate, and wherein the diffusion break region electrically separates the pair of active semiconductor layers from each other.

2. The IC structure of claim 1, wherein the insulative structure includes a low-k dielectric material different from a composition of the set of STIs and the ILD.

3. The IC structure of claim 1, wherein each of the pair of active semiconductor layers comprise portions of a respective nanosheet transistor.

4. The IC structure of claim 1, wherein each of the pair of active semiconductor layers comprise portions of a respective FinFET transistor.

5. The IC structure of claim 1, wherein the diffusion break region comprises a single diffusion break (SDB) region, and wherein the pair of active semiconductor layers comprise portions of a set of logic transistors.

6. The IC structure of claim 1, wherein the diffusion break region comprises a double diffusion break (DDB) region, and wherein the pair of active semiconductor layers comprise portions of a set of memory transistors.

7. The IC structure of claim 1, further comprising a pair of spacers alongside opposing sidewalls of the isolation layer, wherein at least a portion of the pair of active semiconductor layers is positioned above the pair of spacers.

8. An integrated circuit (IC) structure comprising:

a substrate;

a set of shallow trench isolations (STIs) adjacent opposing sidewalls of the substrate;

an insulative structure overlying the substrate, the insulative structure including;

an isolation layer contacting an upper surface of the substrate, and

a diffusion break region integral with and extending from the isolation layer, wherein the diffusion break region horizontally separates a pair of upper surfaces of the isolation layer;

a pair of transistors each positioned on a respective one of the pair of upper surfaces of the isolation layer, each transistor being adjacent an opposing sidewall of the diffusion break region, wherein each of the pair of transistors includes;

a nanosheet stack above the isolation layer, the nanosheet stack including a plurality of semiconductor nanosheets alternating with a plurality of gate metals,

a gate region around the nanosheet stack, the gate region including a gate metal,

a pair of semiconductor terminals, each semiconductor terminal adjacent a respective sidewall of the nanosheet stack, and

a spacer layer horizontally between one of the pair of active semiconductor layers and the diffusion break region; and

an inter-level dielectric (ILD) over the STI and adjacent opposing sidewalls of the insulative structure and the pair of transistors;

wherein the isolation layer electrically separates the pair of transistors from the substrate, and wherein the diffusion break region electrically separates the pair of transistors from each other.

9. The IC structure of claim 8, wherein the insulative structure includes a dielectric material different from a composition of the set of STIs and the ILD.

10. The IC structure of claim 8, wherein the diffusion break region comprises a single diffusion break (SDB) region, and wherein the pair of transistors comprises a set of logic transistors.

11. The IC structure of claim 8, wherein the diffusion break region comprises a double diffusion break (DDB) region, and wherein the pair of transistors comprises a set of memory transistors.

12. The IC structure of claim 8, further comprising a pair of spacers alongside opposing sidewalls of the isolation layer, wherein at least a portion of the pair of semiconductor terminals is positioned on the pair of spacers.

13. The IC structure of claim 8, wherein a vertical height of the isolation layer between the substrate and the pair of transistors is at most approximately ten nanometers (nm), and a horizontal width of the diffusion break region between the pair of transistors is at most approximately fifteen nanometers (nm).

14. The IC structure of claim 8, further comprising an active semiconductor layer vertically between the isolation layer and one of the pair of semiconductor terminals, and horizontally adjacent the spacer layer.

15. A method of forming an integrated circuit (IC) structure, the method comprising:

providing a precursor structure including;

a substrate,

a set of shallow trench isolations (STIs) adjacent opposing sidewalls of the substrate,

a sacrificial material on the substrate, the sacrificial material having a different composition from the substrate,

a plurality of active semiconductor layers on an upper surface of the sacrificial material, the plurality of active semiconductor layers being horizontally separated from each other,

a plurality of nanosheet stacks over the sacrificial material and extending between adjacent pairs of the plurality of semiconductor terminals,

a plurality of gate stacks, each formed around a respective one of the plurality of nanosheet stacks;

forming a cavity within the precursor structure, wherein the forming includes;

forming a first portion of the cavity by removing;

one of the plurality of semiconductor terminals, or one plurality of gate stacks and an underlying one of the plurality of nanosheet stacks, to expose a portion of the sacrificial material, and

forming a second portion of the cavity vertically between the substrate and each of the plurality of semiconductor terminals and the plurality of nanosheet stacks by selectively removing the sacrificial material; and

forming an insulative structure within the first and second portions of the cavity.

16. The method of claim 15, wherein one of the active semiconductor layers includes a plurality of semiconductor nanosheets alternating with a plurality of sacrificial nanosheets, and further comprising removing the plurality of sacrificial nanosheets after forming the insulative structure.

17. The method of claim 16, further comprising forming a plurality of gate metal layers between the plurality of semiconductor nanosheets, after removing the plurality of sacrificial layers.

18. The method of claim 15, wherein forming the cavity further includes:

forming an organic planarizing layer (OPL) over the sacrificial material after forming the first portion of the cavity;

forming a third portion of the cavity by removing the other of one of the portion of the STI and the underlying one of the plurality of semiconductor terminals, or one plurality of gate stacks and the underlying one of the plurality of nanosheet stacks, to expose another underlying portion of the sacrificial material;

removing the OPL after forming the third portion of the cavity; and

forming the insulative structure within the third portion of the cavity.

19. The method of claim 15, further comprising:

replacing a remaining subset of the plurality of gate stacks with a metal gate after forming the insulative structure; and

forming source and drain contacts to a remaining subset of the plurality of semiconductor terminals after forming the insulative structure.

20. The method of claim 15, wherein the sacrificial material includes silicon germanium (SiGe), and wherein forming the second portion of the cavity includes selectively etching the SiGe.