Semiconductor device and manufacturing method thereof

• US 10,665,684 B2
• Filed: 11/05/2018
• Issued: 05/26/2020
• Est. Priority Date: 11/07/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Akimoto, Kengo, Kawae, Daisuke
• Primary Examiner(s): Smith, Zandra V
• Assistant Examiner(s): Joy, Jeremy J
• Application Number:
  US16/180,580
• Publication Number:
  US 20190074361A1
• Time in Patent Office: 568 Days
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/46 Field-effect transistors, e.g. organic thin-film transistors [OTFT] H10K10/43 takes precedence
• CPC Class Codes: H10K 10/462 Insulated gate field-effect transistors [IGFETs]
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/84 Ohmic electrodes, e.g. source or drain electrodes

Abstract

A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Claims

1. A semiconductor device comprising:

a substrate;

a gate electrode over the substrate;

a gate insulating layer over the gate electrode;

a first semiconductor layer over and in direct contact with the gate insulating layer; and

a source electrode and a drain electrode each over the gate insulating layer and electrically connected to the first semiconductor layer;

wherein a first angle formed between an upper surface of the substrate and an upper end portion of a side surface of the source electrode is greater than a second angle formed between the upper surface of the substrate and a lower end portion of the side surface of the source electrode, and

wherein a third angle formed between the upper surface of the substrate and an upper end portion of a side surface of the drain electrode is greater than a fourth angle formed between the upper surface of the substrate and a lower end portion of the side surface of the drain electrode.

2. The semiconductor device according to claim 1, wherein the first semiconductor layer is a first oxide semiconductor layer comprising indium, gallium, and zinc.

3. The semiconductor device according to claim 1, wherein the source electrode and the drain electrode are in direct contact with the gate insulating layer.

4. The semiconductor device according to claim 1, wherein part of the first semiconductor layer is positioned between the side surface of the source electrode and the side surface of the drain electrode.

5. The semiconductor device according to claim 1, further comprising:

a second oxide semiconductor layer over and in direct contact with the source electrode; and

a third oxide semiconductor layer over and in direct contact with the drain electrode,

wherein the second oxide semiconductor layer and the third oxide semiconductor layer have lower resistance than the first semiconductor layer.

6. The semiconductor device according to claim 5, wherein the first semiconductor layer is over and in direct contact with the second oxide semiconductor layer and the third oxide semiconductor layer.

7. The semiconductor device according to claim 5, wherein the second oxide semiconductor layer and the third oxide semiconductor layer each comprise indium, gallium, and zinc.

8. The semiconductor device according to claim 1, wherein each of the source electrode and the drain electrode is a single layer.

9. The semiconductor device according to claim 1, wherein each of the second angle and the fourth angle is greater than or equal to 20°

and less than 90°

.

10. The semiconductor device according to claim 1, wherein each of the first angle and the third angle is 90°

.

11. The semiconductor device according to claim 1, further comprising a pixel electrode electrically connected to the source electrode or the drain electrode.

12. A semiconductor device comprising:

an n-channel transistor comprising;

a gate electrode over a substrate;

a gate insulating layer over the gate electrode;

a first oxide semiconductor layer over and in direct contact with the gate insulating layer;

a source electrode and a drain electrode each over the gate insulating layer and electrically connected to the first oxide semiconductor layer;

a first oxide film on a side surface of the source electrode; and

a second oxide film on a side surface of the drain electrode,

wherein a first angle formed between an upper surface of the substrate and an upper end portion of the side surface of the source electrode is greater than a second angle formed between the upper surface of the substrate and a lower end portion of the side surface of the source electrode,

wherein a third angle formed between the upper surface of the substrate and an upper end portion of the side surface of the drain electrode is greater than a fourth angle formed between the upper surface of the substrate and a lower end portion of the side surface of the drain electrode, and

wherein the lower end portion of the source electrode and the lower end portion of the drain electrode are in contact with the first oxide semiconductor layer.

13. The semiconductor device according to claim 12, wherein the first oxide semiconductor layer comprises indium, gallium, and zinc.

14. The semiconductor device according to claim 12, wherein the source electrode and the drain electrode are in direct contact with the gate insulating layer.

15. The semiconductor device according to claim 12, wherein part of the first oxide semiconductor layer is positioned between the side surface of the source electrode and the side surface of the drain electrode.

16. The semiconductor device according to claim 12, further comprising:

a second oxide semiconductor layer over and in direct contact with the source electrode; and

a third oxide semiconductor layer over and in direct contact with the drain electrode,

wherein the second oxide semiconductor layer and the third oxide semiconductor layer have lower resistance than the first oxide semiconductor layer.

17. The semiconductor device according to claim 16, wherein the first oxide semiconductor layer is over and in direct contact with the second oxide semiconductor layer and the third oxide semiconductor layer.

18. The semiconductor device according to claim 16, wherein the second oxide semiconductor layer and the third oxide semiconductor layer each comprise indium, gallium, and zinc.

19. The semiconductor device according to claim 12, wherein each of the source electrode and the drain electrode is a single layer.

20. The semiconductor device according to claim 12, wherein each of the second angle and the fourth angle is greater than or equal to 20°

and less than 90°

.

21. The semiconductor device according to claim 12, wherein each of the first angle and the third angle is 90°

.

22. The semiconductor device according to claim 12, wherein each of the first oxide film and the second oxide film is a native oxide film.