Gate feature in finFET device

• US 10,665,686 B2
• Filed: 04/08/2019
• Issued: 05/26/2020
• Est. Priority Date: 07/18/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shen, Guan-Jie, Chang, Chia-Der, Lin, Chih-Hsiung
• Primary Examiner(s): Naraghi, Ali
• Application Number:
  US16/378,342
• Publication Number:
  US 20190237555A1
• Time in Patent Office: 414 Days
• Field of Search: None
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a fin structure, disposed on a substrate, that horizontally extends along a direction; and a gate feature comprising a gate dielectric layer and at least a first metal gate layer overlaying the gate dielectric layer, wherein the gate dielectric layer and the first metal gate layer traverse the fin structure to overlay a central portion of the fin structure and further extend along the direction to overlay at least a side portion of the fin structure that is located outside a vertical projection of a sidewall of the gate feature.

Claims

1. A method for forming a fin field-effect transistor (FinFET), comprising:

forming a fin structure protruding a major surface of a substrate;

exposing an upper portion of the fin structure by surrounding a lower portion of the fin structure;

forming a dummy poly layer over the upper portion of the fin structure;

etching an upper side portion of the dummy poly layer using a first etching process;

etching a lower side portion of the dummy poly layer using a second etching process thereby exposing an end portion of the upper portion of the fin and forming a poly footing feature that extends beyond a vertical sidewall of a remaining portion of the dummy poly layer;

forming a dielectric layer over the exposed end portion and along the vertical sidewall; and

removing the remaining portion of the dummy poly layer and the poly footing feature thereby forming a void to expose a central portion and a side portion of the upper portion of the fin structure, wherein the side portion extends beyond a vertical projection of the vertical sidewall.

2. The method of claim 1, further comprising:

filling the void with a high-k dielectric layer to surround a top surface and sidewalls of the central portion and side portion of the upper portion of the fin structure.

3. The method of claim 2, further comprising:

filling the void with a metal gate layer to overlay the high-k dielectric layer.

4. The method of claim 1, further comprising forming a gate feature to overlay the central portion of the upper portion of the fin structure.

5. The method of claim 4, wherein the gate feature comprises a gate dielectric layer and at least a metal gate layer.

6. The method of claim 5, wherein the gate dielectric layer comprises a high-k dielectric layer.

7. The method of claim 4, wherein the gate feature surrounds sidewalls and a top surface of the central portion of the upper portion of the fin structure.

8. The method of claim 4, wherein the gate feature surrounds sidewalls and a top surface of the side portion of the upper portion of the fin structure.

9. The method of claim 4, further comprising forming a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature.

10. The method of claim 4, further comprising forming an oxide layer between the fin structure and the gate feature.

11. A method of making a semiconductor device, comprising:

forming a fin structure on a substrate; and

forming a gate feature over the fin structure, the gate feature comprising a gate dielectric layer and at least a first metal gate layer overlaying the gate dielectric layer, wherein the gate dielectric layer and the first metal gate layer traverse the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.

12. The method of claim 11, wherein the gate dielectric layer comprises a high-k dielectric layer.

13. The method of claim 11, wherein the gate feature comprises one or more metal gate layers, stacked on top to one another, on the first metal gate layer.

14. The method of claim 11, wherein the gate dielectric layer and the first metal gate layer surround sidewalls and a top surface of the central portion of the fin structure.

15. The method of claim 11, further comprising forming a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature.

16. The method of claim 11, further comprising forming an oxide layer disposed between the fin structure and the gate feature.

17. A method of making a semiconductor device, comprising:

forming a fin structure on a substrate;

forming a gate feature that traverses the fin structure to overlay a central portion of the fin structure;

forming a dielectric layer adjacent to opposite sidewalls of the gate feature;

forming undercuts in respective portions of the dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend away from respective sidewalls of the gate feature and away from the central portion of the fin structure, and wherein the gate feature further extends along the fin structure to overlay opposite side portions of the fin structure located in respective undercuts;

forming a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and

forming an oxide layer disposed between the fin structure and the gate feature.

18. The method of claim 17, wherein the gate feature comprises a gate dielectric layer and at least a metal gate layer.

19. The method of claim 18, wherein the gate dielectric layer comprises a high-k dielectric layer.

20. The method of claim 18, wherein the gate dielectric layer and the first metal gate layer surround sidewalls and top surfaces of the central portion and the side portions of the fin structure.