×

Non-self aligned gate contacts formed over the active region of a transistor

  • US 10,665,692 B2
  • Filed: 10/24/2018
  • Issued: 05/26/2020
  • Est. Priority Date: 10/24/2018
  • Status: Active Grant
First Claim
Patent Images

1. A method for forming a silicon structure, the method comprising:

  • forming a trench silicide contact between two spacers, each spacer beside respective high-k metal gates;

    planarizing the trench silicide contact, the spacers, and the high-k metal gates;

    depositing an inner layer dielectric over the trench silicide contact, the spacers, and the high-k metal gates;

    patterning a first opening in the inner layer dielectric for a gate contact over the high-k metal gate, one of the spacers and a portion of the trench silicide contact;

    recessing the portion of the trench silicide contact;

    depositing a liner within the recessed portion of the trench silicide contact and on sidewalls of the first opening of the inner layer dielectric; and

    depositing a metallization layer in the opening in the inner layer dielectric to form the gate contact.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×