Non-self aligned gate contacts formed over the active region of a transistor

• US 10,665,692 B2
• Filed: 10/24/2018
• Issued: 05/26/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Xie, Ruilong, Park, Chanro, Cheng, Kangguo, Frougier, Julien
• Primary Examiner(s): Ho, Anthony
• Application Number:
  US16/169,161
• Publication Number:
  US 20200135885A1
• Time in Patent Office: 580 Days
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/823443 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for forming a silicon structure. The method includes forming a trench silicide contact between two spacers, each spacer beside respective high-k metal gates. The method planarizes the trench silicide contact, the spacers, and the high-k metal gates. An inner layer dielectric is deposited over the trench silicide contact, the spacers, and the high-k metal gates. A first opening is patterned in the inner layer dielectric for a gate contact over the high-k metal gate, one of the spacers and a portion of the trench silicide contact. The method recesses the portion of the trench silicide contact and deposits a liner within the recessed portion of the trench silicide contact and on sidewalls of the first opening of the inner layer dielectric. A metallization layer is deposited in the opening in the inner layer dielectric to form the gate contact.

Claims

1. A method for forming a silicon structure, the method comprising:

forming a trench silicide contact between two spacers, each spacer beside respective high-k metal gates;

planarizing the trench silicide contact, the spacers, and the high-k metal gates;

depositing an inner layer dielectric over the trench silicide contact, the spacers, and the high-k metal gates;

patterning a first opening in the inner layer dielectric for a gate contact over the high-k metal gate, one of the spacers and a portion of the trench silicide contact;

recessing the portion of the trench silicide contact;

depositing a liner within the recessed portion of the trench silicide contact and on sidewalls of the first opening of the inner layer dielectric; and

depositing a metallization layer in the opening in the inner layer dielectric to form the gate contact.

2. The method of claim 1, further comprising patterning a second opening in the inner layer dielectric for a source/drain contact over the trench silicide contact, the other one of the spacers, and a portion of the high-k metal gate.

3. The method of claim 2, further comprising recessing the portion of the high-k metal gate.

4. The method of claim 3, wherein the liner is further deposited on sidewalls of the second opening of the inner layer dielectric and within the recessed portion of the high-k metal gate.

5. The method of claim 4, further comprising depositing the metallization layer in the second opening in the inner layer dielectric to form the source/drain contact.

6. The method of claim 1, wherein depositing a liner within the recessed portion of the trench contact and on sidewalls of the first opening of the inner layer dielectric, further comprises depositing the liner on top of the inner layer dielectric and on the high-k metal gate.

7. The method of claim 6, further comprising removing the liner from the top of the inner layer dielectric and the high-k metal gate.

8. The method of claim 2, further comprising, prior to patterning the second opening, depositing an organic planarization layer over the inner layer dielectric and within the first opening.

9. The method of claim 8, further comprising, removing the organic planarization layer before depositing the liner.

10. The method of claim 1, wherein forming a trench silicide contact between two spacers, each spacer beside respective high-k metal gates, comprises depositing an organic planarization layer on one of the spacers and at least a portion of the high-k metal gate.

11. The method of claim 10, wherein forming a trench silicide contact between two spacers further comprises etching away an inner layer dielectric disposed between the two spacers.

12. The method of claim 11, wherein forming a trench silicide contact between two spacers, further comprises removing the organic planarization layer by ashing the organic planarization layer.

13. The method of claim 12, wherein forming a trench silicide contact between two spacers, further comprises overfilling the opening left behind by etching away the inner layer dielectric with a metal.

14. The method of claim 13, wherein the metal is selected from the group consisting of silicide, cobalt, or tungsten.