3D semiconductor device with isolation layers

• US 10,665,695 B2
• Filed: 08/09/2019
• Issued: 05/26/2020
• Est. Priority Date: 04/09/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian
• Primary Examiner(s): Blum, David S
• Application Number:
  US16/536,606
• Publication Number:
  US 20190363179A1
• Time in Patent Office: 291 Days
• Field of Search: 257 43, 257368, 257369, 257456, 257497, 257499
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66901 : with a PN homojunction gate
• CPC Class Codes: H01L 29/732 : Vertical transistors
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7841 : with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 29/808 : with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H10B 12/09 : with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor

Abstract

A 3D semiconductor device, the device including: a first level including single crystal first transistors, where the first level is overlaid by a first isolation layer; a second level including single crystal second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, and where the first isolation layer and the second isolation layer are separated by a distance of less than four microns.

Claims

1. A 3D semiconductor device, the device comprising:

a first level comprising single crystal first transistors,

wherein said first level is overlaid by a first isolation layer;

a second level comprising single crystal second transistors,

wherein said first isolation layer is overlaid by said second level, and

wherein said second level is overlaid by a second isolation layer;

a third level comprising single crystal third transistors,

wherein said second isolation layer is overlaid by said third level,

wherein said third level is overlaid by a third isolation layer, and

wherein said first isolation layer and said second isolation layer are separated by a distance of less than four microns.

2. The device according to claim 1,

wherein said distance is less than two microns.

3. The device according to claim 1, further comprising:

a connective path between said third transistors and said second transistors,

wherein said connective path comprises a via through said second isolation, and

wherein said via has a diameter of less than 400 nm.

4. The device according to claim 1, further comprising:

a heat removal path from said second transistors to an external surface of said device.

5. The device according to claim 1, further comprising:

a power delivery path to said second transistors,

wherein at least a portion of said power delivery path is underneath at least one of said second transistors.

6. The device according to claim 1,

wherein misalignment between said third transistors and said second transistors is less than 100 nm.

7. The device according to claim 1, further comprising:

first connections to external devices; and

second connections to external devices,

wherein at least a portion of said first connections are underneath said first isolation layer, and

wherein at least a portion of said second connections are above said third isolation layer.

8. A 3D semiconductor device, the device comprising:

a first level comprising single crystal first transistors,

wherein said first level is overlaid by a first isolation layer;

a second level comprising single crystal second transistors,

wherein said first isolation layer is overlaid by said second level, and

wherein said second level is overlaid by a second isolation layer;

a third level comprising single crystal third transistors,

wherein said second isolation layer is overlaid by said third level,

wherein said third level is overlaid by a third isolation layer; and

a connective path from said third transistors to said second transistors,

wherein said connective path comprises a via through said second isolation, and

wherein said via has a diameter of less than 400 nm.

9. The device according to claim 8,

wherein said first isolation layer and said second isolation layer are separated by a distance of less than two microns.

10. The device according to claim 8,

wherein a majority of said second level comprises memory.

11. The device according to claim 8, further comprising:

a heat removal path from said second transistors to an external surface of said device.

12. The device according to claim 8, further comprising:

a power delivery path to said second transistors,

wherein at least a portion of said power delivery path is underneath at least one of said second transistors.

13. The device according to claim 8,

wherein misalignment between said third transistors and said second transistors is less than 100 nm.

14. The device according to claim 8, further comprising:

first connections to at least one external device; and

second connections to at least one external device,

wherein at least a portion of said first connections are underneath said first isolation layer, and

wherein at least a portion of said second connections are above said third isolation layer.

15. A 3D semiconductor device, the device comprising:

a first level comprising single crystal first transistors,

wherein said first level is overlaid by a first isolation layer;

a second level comprising single crystal second transistors,

wherein said first isolation layer is overlaid by said second level, and

wherein said second level is overlaid by a second isolation layer;

a third level comprising single crystal third transistors,

wherein said second isolation layer is overlaid by said third level,

wherein said third level is overlaid by a third isolation layer, and

wherein misalignment between said third transistors and said second transistors is less than 100 nm.

16. The device according to claim 15,

wherein said first isolation layer and said second isolation layer are separated by a distance of less than four microns.

17. The device according to claim 15, further comprising:

a connective path from said third transistors to said second transistors,

wherein said connective path comprises a via through said second isolation, and

wherein said via has a diameter of less than 400 nm.

18. The device according to claim 15, further comprising:

a heat removal path from said second transistors to an external surface of said device.

19. The device according to claim 15, further comprising:

a power delivery path to said second transistors,

wherein at least a portion of said power delivery path is underneath at least one of said second transistors.

20. The device according to claim 15, further comprising:

first connections to at least one external device; and

second connections to at least one external device,

wherein at least a portion of said first connections are underneath said first isolation layer, and

wherein at least a portion of said second connections are above said third isolation layer.