Semiconductor device having channel regions

• US 10,665,723 B2
• Filed: 10/16/2018
• Issued: 05/26/2020
• Est. Priority Date: 01/04/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Seung Min, Park, Woo Seok, Bae, Geum Jong, Bae, Dong Il, Yang, Jung Gil
• Primary Examiner(s): Stark, Jarrett J
• Application Number:
  US16/161,765
• Publication Number:
  US 20190088789A1
• Time in Patent Office: 588 Days
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes a substrate; protruding portions extending in parallel to each other on the substrate; nanowires provided on the protruding portions and separated from each other; gate electrodes provided on the substrate and surrounding the nanowires; source/drain regions provided on the protruding portions and sides of each of the gate electrodes, the source/drain regions being in contact with the nanowires; and first voids provided between the source/drain regions and the protruding portions.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

stacking semiconductor layers on a substrate;

removing portions of the semiconductor layers and the substrate to form fin structures, the fin structures including protruding portions of the substrate and remaining portions of the semiconductor layers stacked on the protruding portions;

removing portions of the fin structures to form nanowires from the remaining portions of the semiconductor layers, the nanowires being separated from each other;

forming source/drain regions between and in contact with the nanowires, wherein first voids are formed between the source/drain regions and the substrate; and

forming gate electrodes surrounding the nanowires.

2. The method of claim 1, wherein the stacking semiconductor layers on the substrate comprises alternately stacking the semiconductor layers and sacrificial layers on the substrate, and

wherein the method further comprises, after the removing the portions of the fin structures, removing portions of the sacrificial layers in regions from which the fin structures have been removed to form side spaces and filling the side spaces with an insulating material to form inner spacers between the nanowires and between a lowermost nanowire among the nanowires and the substrate.

3. The method of claim 2, wherein, in a cross section taken in a first direction in which the protruding portions are extended, the first voids are sealed by the source/drain regions, the protruding portions, and lowermost inner spacers of the inner spacers.

4. The method of claim 1, wherein a lower surface of each of the source/drain regions is lower than a lower surface of each of lowermost nanowires among of the nanowires.

5. The method of claim 1, further comprising forming an isolation insulating layer on the substrate, the isolation insulating layer covering a portion of a side surface of the protruding portions.