Phase noise reduction in voltage controlled oscillators
First Claim
1. A design structure comprising:
- a machine readable hardware medium having machine readable instructions tangibly embodied therein for design, manufacturing, or testing a semiconductor device, the machine readable instructions executable by a computer design system to cause the computer design system;
to generate a machine readable representation of a voltage controlled oscillator (VCO), said machine readable representation being encoded in a machine readable hardware storage media;
said encoded machine readable representation comprising;
encoded machine readable representation of an LC tank circuit for generating an oscillator output signal at an oscillator frequency (fo);
encoded machine readable representation of an oscillator core including first and second cross-coupled semiconductor devices connected to the tank circuit to provide regenerative feedback to the tank circuit to help maintain the oscillator output stable;
a encoded machine readable representation of a supply node connected to the oscillator core for connecting the VCO to a voltage source;
encoded machine readable representation of a tail node connected to the oscillator core for connecting the VCO to a current source; and
encoded machine readable representation of a noise by-pass circuit connected to the supply node and to the tail node, in parallel with the LC tank circuit and the oscillator core, and forming a low-impedance path at a frequency approximately twice the oscillator frequency to at least partially immunize the oscillator core from external noise and to reduce noise contribution from the cross-coupled semiconductor devices; and
wherein the computer design system includes a lithography machine for generating masks.
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Accused Products
Abstract
A voltage controlled oscillator (VCO), a method of designing a voltage controlled oscillator, and a design structure comprising a semiconductor substrate including a voltage controlled oscillator are disclosed. In one embodiment, the VCO comprises an LC tank circuit for generating an oscillator output at an oscillator frequency, and an oscillator core including cross-coupled semiconductor devices to provide feedback to the tank circuit. The VCO further comprises a supply node, a tail node, and a noise by-pass circuit connected to the supply and tail nodes, in parallel with the tank circuit and the oscillator core. The by-pass circuit forms a low-impedance path at a frequency approximately twice the oscillator frequency to at least partially immunize the oscillator core from external noise and to reduce noise contribution from the cross-coupled semiconductor devices.
24 Citations
8 Claims
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1. A design structure comprising:
a machine readable hardware medium having machine readable instructions tangibly embodied therein for design, manufacturing, or testing a semiconductor device, the machine readable instructions executable by a computer design system to cause the computer design system; to generate a machine readable representation of a voltage controlled oscillator (VCO), said machine readable representation being encoded in a machine readable hardware storage media; said encoded machine readable representation comprising; encoded machine readable representation of an LC tank circuit for generating an oscillator output signal at an oscillator frequency (fo); encoded machine readable representation of an oscillator core including first and second cross-coupled semiconductor devices connected to the tank circuit to provide regenerative feedback to the tank circuit to help maintain the oscillator output stable; a encoded machine readable representation of a supply node connected to the oscillator core for connecting the VCO to a voltage source; encoded machine readable representation of a tail node connected to the oscillator core for connecting the VCO to a current source; and encoded machine readable representation of a noise by-pass circuit connected to the supply node and to the tail node, in parallel with the LC tank circuit and the oscillator core, and forming a low-impedance path at a frequency approximately twice the oscillator frequency to at least partially immunize the oscillator core from external noise and to reduce noise contribution from the cross-coupled semiconductor devices; and wherein the computer design system includes a lithography machine for generating masks. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A computer design system comprising:
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a lithography machine for generating masks; and a machine readable hardware medium having machine readable instructions tangibly embodied therein for designing a semiconductor device, the machine readable instructions executable by the computer design system to instantiate a design of a voltage controlled oscillator in a programmable gate array, the instantiated design comprising; a machine readable representation, encoded in the programmable gate array, of an LC tank circuit for generating an oscillator output signal at an oscillator frequency (fo); a machine readable representation, encoded in the programmable gate array, of an oscillator core including first and second cross-coupled semiconductor devices connected to the tank circuit to provide regenerative feedback to the tank circuit to help maintain the oscillator output stable; a machine readable representation, encoded in the programmable gate array, of a supply node connected to the oscillator core for connecting the VCO to a voltage source; a machine readable representation, encoded in the programmable gate array, of a tail node connected to the oscillator core for connecting the VCO to a current source; and a machine readable representation, encoded in the programmable gate array, of a noise by-pass circuit connected to the supply node and to the tail node, in parallel with the LC tank circuit and the oscillator core, and forming a low-impedance path at a frequency approximately twice the oscillator frequency to at least partially immunize the oscillator core from external noise and to reduce noise contribution from the cross-coupled semiconductor devices.
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Specification