Pipelined forward error correction for vector signaling code channel

• US 10,666,297 B2
• Filed: 04/16/2018
• Issued: 05/26/2020
• Est. Priority Date: 04/14/2017
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Shokrollahi, Amin, Carnelli, Dario
• Primary Examiner(s): Kerveros, James C
• Application Number:
  US15/954,138
• Publication Number:
  US 20180302106A1
• Time in Patent Office: 771 Days
• Field of Search: 714776
• CPC Class Codes: H03M 13/091 Parallel or block-wise CRC computation
• CPC Class Codes: H03M 13/134 Non-binary linear block codes not provided for otherwise
• CPC Class Codes: H03M 13/1575 Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/3746 with iterative decoding
• CPC Class Codes: H03M 13/616 Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
• CPC Class Codes: H03M 13/6561 Parallelized implementations
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0061 Error detection codes

Abstract

Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

Claims

1. A method comprising:

generating, using a vector signal code receiver, a plurality of linear combinations of wire signals present on a plurality of wires to decode a predetermined number of sequentially received vector signaling codewords to obtain (i) sequential sets of data bits and (ii) two multi-bit error correction check words, wherein elements of each vector signaling codeword correspond to the wire signals and are received in parallel over the plurality of wires, wherein each linear combination of the plurality of linear combinations is defined by a respective sub-channel of a plurality of mutually orthogonal sub-channels;

generating, using a forward error correction (FEC) check circuit, an incremental update of two multi-bit error correction syndrome values based on each sequential set of data bits according to a check matrix, wherein each bit of a first multi-bit error correction syndrome value of the two multi-bit error correction syndrome values is incrementally updated using bits from corresponding bit positions in each set of data bits of the sequential sets of data bits;

upon decoding of a final vector signaling codeword of the predetermined number of received vector signaling codewords, performing a final incremental update of the two multi-bit error correction syndrome values, the final incremental update including bitwise-comparisons of each multi-bit error correction syndrome value to a respective multi-bit error correction check word of the two multi-bit error correction check words;

selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from a combination of the two multi-bit error correction syndrome values; and

altering the selected set of data bits according to a bit error mask corresponding to the first multi-bit error correction syndrome value of the two multi-bit error correction syndrome values.

2. The method of claim 1, wherein generating the incremental updates of the two multi-bit error correction syndrome values comprises performing a logical XOR operation on a previously-stored multi-bit error correction syndrome value based on a given set of data bits of the sequential sets of data bits.

3. The method of claim 1, wherein the two multi-bit error correction syndrome values are initialized to logic zero values.

4. The method of claim 1, wherein the two error correction syndrome values are initialized according to the multi-bit error correction check words prior to generating the incremental updates of the two multi-bit error correction syndrome values.

5. The method of claim 1, wherein the symbol position index is determined by forming a binary reciprocal of the first multi-bit error correction syndrome value, and forming a modulo-reduced multiplication with a second multi-bit error correction syndrome value of the two multi-bit error correction syndrome values.

6. The method of claim 5, wherein the binary reciprocal is formed using a lookup table (LUT).

7. The method of claim 1, wherein the first multi-bit error correction syndrome value is updated by performing a logical XOR function on the bits from the corresponding bit positions in the sequential sets of data bits sharing a common bit position.

8. The method of claim 1, wherein the selected set of data bits is altered by performing a bit-wise XOR of the selected set of data bits with the bit error mask to create a corrected set of data bits.

9. The method of claim 8, wherein the sequential sets of data bits are stored in a first register, and wherein the bit error mask is stored in a second register, and wherein the corrected set of data bits are stored in a third register.

10. The method of claim 9, wherein the symbol position index identifies a location in the second register to store the bit error mask.

11. An apparatus comprising:

a vector signal code receiver configured to generate a plurality of linear combinations of wire signals present on a plurality of wires to decode a predetermined number of sequentially received vector signaling codewords to obtain (i) sequential sets of data bits and (ii) two multi-bit error correction check words, wherein elements of each vector signaling codeword correspond to the wire signals and are received in parallel over the plurality of wires, each linear combination of the plurality of linear combinations defined by a respective sub-channel of a plurality of mutually orthogonal sub-channels;

a forward error correction (FEC) check circuit configured to;

generate an incremental update of two error correction syndrome values based on each sequential set of data bits according to a check matrix, wherein each bit of a first multi-bit error correction syndrome value of the two multi-bit error correction syndrome values is incrementally updated using bits from corresponding bit positions in the sequential sets of data bits; and

in response to decoding of a final vector signaling codeword of the predetermined number of received vector signaling codewords, perform a final incremental update of the two multi-bit error correction syndrome values, the final incremental update including bitwise-comparisons of each multi-bit error correction syndrome value to a respective multi-bit error correction check word of the two multi-bit error correction check words; and

an error correction circuit configured to select a set of data bits from the sequential sets of data bits according to a symbol position index determined from a combination of the two multi-bit error correction syndrome values, and to responsively alter the selected set of data bits according to a bit error mask corresponding to the first multi-bit error correction syndrome value of the two multi-bit error correction syndrome values.

12. The apparatus of claim 11, wherein the FEC check circuit is configured to generate the incremental updates of the two multi-bit error correction syndrome values by performing a logical XOR operation on a previously-stored multi-bit error correction syndrome value based on a given set of data bits of the sequential sets of data bits.

13. The apparatus of claim 11, wherein the two multi-bit error correction syndrome values are initialized to logic zero values.

14. The apparatus of claim 11, wherein the two multi-bit error correction syndrome values are initialized according to the two multi-bit error correction check words prior to the FEC check circuit generating the incremental updates of the two multi-bit error correction syndrome values.

15. The apparatus of claim 11, wherein the error correction circuit is configured to determine the symbol position index by forming a binary reciprocal of the first multi-bit error correction syndrome value and forming a modulo-reduced multiplication with a second multi-bit error correction syndrome value of the two error correction syndrome values.

16. The apparatus of claim 15, wherein the binary reciprocal is formed using a lookup table (LUT).

17. The apparatus of claim 11, wherein the FEC check circuit is configured to update the first multi-bit error correction syndrome value by performing a logical XOR function on the bits from corresponding bit positions in the sequential sets of data bits.

18. The apparatus of claim 11, wherein the error correction circuit is configured to alter the selected set of data bits by performing a bit-wise XOR of the selected set of data bits with the bit error mask to create a corrected set of data bits.

19. The apparatus of claim 18, wherein the error correction circuit comprises a first register configured to store the sequential sets of data bits, a second register configured to store the bit error mask, and a third register configured to store the corrected set of data bits.

20. The apparatus of claim 19, wherein the symbol position index identifies a location in the second register to store the bit error mask.