Synchronized parallel tile computation for large area lithography simulation

• US 10,671,052 B2
• Filed: 01/10/2018
• Issued: 06/02/2020
• Est. Priority Date: 11/15/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Beylkin, Daniel, Ho, Kenneth L., Trivedi, Sagar Vinodbhai, Xu, Fangbo, Lei, Junjiang, Peng, Danping
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US15/867,437
• Publication Number:
  US 20190146455A1
• Time in Patent Office: 874 Days
• Field of Search: 716 55, 716 54, 716 51, 382144, 382145, 382154
• CPC Class Codes: G03F 1/24 Reflection masks; Preparation thereof
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G05B 19/4097 characterised by using design data to control NC machines, e.g. CAD/CAM G05B19/4093 takes precedence
• CPC Class Codes: G05B 2219/35012 Cad cam
• CPC Class Codes: G05B 2219/45027 Masking, project image on wafer semiconductor, photo tracer
• CPC Class Codes: G05B 2219/45028 Lithography
• CPC Class Codes: G05B 2219/45031 Manufacturing semiconductor wafers
• CPC Class Codes: G06F 2111/20 Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G21K 5/00 Irradiation devices discharge tubes for irradiating H01J37/00
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

Claims

1. A method for lithography simulation, the method comprising:

receiving a simulation box of an IC design layout by a first worker machine, the simulation box including a first transition region, the first transition region covering a pixel, the pixel also being covered by one or more second transition regions processed by one or more second worker machines;

computing a first pixel value of the pixel to simulate a first stage of a lithography process;

receiving one or more second pixel values that have been computed for the pixel by the one or more second worker machines interacting with the first worker machine; and

computing an updated pixel value of the pixel to simulate a second stage of the lithography process based on a weighted combination of the first pixel value and the one or more second pixel values.

2. The method of claim 1, wherein the weighted combination uses a plurality of weights, each multiplied by one of the first pixel value and the one or more second pixel values in computing the updated pixel value, and wherein a sum of the plurality of weights equals one.

3. The method of claim 1, further comprising transmitting the updated pixel value of the pixel to each of the one or more second worker machines.

4. The method of claim 3, further comprising:

receiving the IC design layout by a manager machine interacting with the first worker machine and with the one or more second worker machines;

partitioning, by the manager machine, the IC design layout into a plurality of simulation boxes including the simulation box;

assigning, by the manager machine, the simulation box to the first worker machine for simulation; and

sending, from the manager machine to the first worker machine, message delivery instructions that specify how the updated pixel value of the pixel is to be transmitted to each of the one or more second worker machines.

5. The method of claim 1, wherein the updated pixel value of the pixel is a first updated pixel value that is computed by the first worker machine, the method further comprising:

receiving one or more third pixel values that have been generated for the pixel by the one or more second worker machines, to simulate the second stage of the lithography process; and

computing a second updated pixel value of the pixel based on a weighted combination of the first updated pixel value and the one or more third pixel values.

6. The method of claim 5, wherein the first stage and the second stage are used for optical proximity correction (OPC), wherein the first updated pixel value of the pixel represents an optical image value at the pixel, and wherein the second updated pixel value of the pixel represents a resist image value at the pixel.

7. The method of claim 5, wherein the first stage and the second stage are used for inverse lithography technology (ILT), wherein the first updated pixel value of the pixel represents a wafer image value at the pixel, and wherein the second updated pixel value of the pixel represents a gradient value at the pixel.

8. The method of claim 5, further comprising:

generating a modified IC design layout based in part on the second updated pixel value; and

providing the modified IC design layout for fabricating a lithography mask based on the modified IC design layout.

9. The method of claim 1, wherein the weighted combination of the first pixel value and the one or more second pixel values is specified by one or more weighting functions, wherein each weighting function accords (a) a weight of one to an core region of the simulation box, (b) weights between zero and one to the first transition region, and (c) a weight of zero to a halo region of the simulation box.

10. The method of claim 1, wherein the simulation box further includes a core region surrounded by the first transition region and a halo region surrounding the first transition region, the method further comprising computing updated pixel values of a plurality of pixels in the core region by using only pixel values that have been generated for the plurality of pixels by the first worker machine, while not using any previous pixel values generated for the plurality of pixels by the one or more second worker machines, and wherein computing the updated pixel value of the pixel is further based on additional pixels located in the halo region, wherein values of the additional pixels located in the halo region are not transmitted by the first worker machine to any of the one or more second worker machines.

11. A method, comprising:

receiving an Integrated Circuit (IC) design layout;

partitioning the IC design layout into a first tile and a second tile, the second tile overlapping with the first tile at a transition region;

computing a first image value of a pixel of the transition region, by a first worker machine, to simulate a first stage of a lithography process;

computing a second image value of the pixel of the transition region, by a second worker machine, to simulate the first stage of the lithography process;

computing an updated image value of the pixel, by the first worker machine, starting from a weighted average of the first image value of the pixel and the second image value of the pixel, to simulate a second stage of the lithography process;

generating a modified IC design layout based in part on the updated image value of the pixel; and

fabricating a mask based on the modified IC design layout.

12. The method of claim 11, wherein the pixel of the transition region is a first pixel, and the first tile includes a second pixel outside the transition region, the method further comprising:

computing an image value of the second pixel, by the first worker machine, to simulate the first stage of the lithography process; and

computing an updated image value of the second pixel, by the first worker machine, to simulate the second stage of the lithography process starting from the image value of the second pixel,

wherein the generating of the modified IC design layout includes generating based in part on the updated image value of the second pixel.

13. The method of claim 11, further comprising:

evaluating the modified IC design layout against pre-set design rules; and

iteratively adjusting the modified IC design layout until the adjusted modified IC design layout satisfies the pre-set design rules.

14. The method of claim 11, wherein the first tile and the second tile are different in shape or size.

15. The method of claim 11, further comprising computing a third image value of the pixel, by a second worker machine, starting from the weighted average, to simulate the second stage of the lithography process using, wherein the generating of the modified IC design layout includes generating based on a weighted combination of the third image value and the updated image value.

16. A method, comprising:

receiving an Integrated Circuit (IC) design layout;

partitioning the IC design layout, by a manager machine, into a plurality of tiles, a first tile and a second tile of the plurality of tiles overlapping with each other to form a transition region;

simulating a first imaging stage of a lithography process, the simulating includes;

generating a first pixel value of a pixel in the transition region at a first worker machine; and

generating a second pixel value of the pixel at a second worker machine;

simulating a second imaging stage of the lithography process, the simulating includes;

computing, by the first worker machine, a weighted combination of the first pixel value and the second pixel value;

generating, by the first worker machine, an updated pixel value from the weighted combination of the first pixel value and the second pixel value;

generating a modified IC design layout based on the simulated second imaging stage; and

fabricating a mask based on the modified IC design layout.

17. The method of claim 16, further comprising exchanging the first pixel value and the second pixel value between the first work machine and the second work machine according to an instruction from the manager machine.

18. The method of claim 16, wherein the weighted combination of the first pixel value and the second pixel value includes a first weight multiplied by the first pixel value and a second weight multiplied by the second pixel value, and wherein a sum of the first weight and the second weight is greater than zero but equal to or less than one.

19. The method of claim 16, wherein the simulating of the first imaging stage is an iterative process used in optical proximity correction (OPC) or inverse lithography technology (ILT), and each iteration of the iterative process includes simulating the first and the second imaging stages, the method further comprising repeatedly performing the iterative process until the modified IC design layout satisfies pre-set conditions.

20. The method of claim 16, wherein the updated pixel value is a first updated pixel value, and wherein the simulating of the second imaging stage of the lithography process further includes:

generating a third pixel value, by the second worker machine, from the weighted combination of the first pixel value and the second pixel value; and

computing a second updated pixel value of the pixel based on a weighted combination of the first updated pixel value and the third pixel value,

wherein the generating of the modified IC design layout based on the simulated second imaging stage includes generating based on the second updated pixel value.