Gate driving circuit and display apparatus having the same

• US 10,671,112 B2
• Filed: 08/15/2019
• Issued: 06/02/2020
• Est. Priority Date: 10/24/2018
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Lee, Whee-Won, Eom, Ji Young
• Primary Examiner(s): Donovan, Lincoln D
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US16/541,904
• Publication Number:
  US 20200133327A1
• Time in Patent Office: 292 Days
• Field of Search: None
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/067 Special waveforms for scanning, where no circuit details of the gate driver are given
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H03C 3/0966 modulating the reference clock

Abstract

A gate driving circuit includes a pull-up control part for applying a first previous carry signal to a first node in response to the first previous carry signal, a first pull-up part outputting a clock signal as an N-th gate output signal in response to a signal applied to the first node, a second pull-up part outputting the clock signal as the N-th gate output signal in response to the signal applied to the first node, a carry part outputting the clock signal as an N-th carry signal in response to the signal applied to the first node, a first pull-down part pulling down the signal at the first node to a second off voltage, and a second pull-down part pulling down the N-th gate output signal to a first off voltage, wherein one of the first pull-up part and the second pull-up part is selectively activated.

Claims

1. A gate driving circuit comprising:

a pull-up control part configured to apply a first previous carry signal, which is a carry signal of one of previous stages, to a first node in response to the first previous carry signal;

a first pull-up part configured to output a clock signal as an N-th gate output signal in response to a signal applied to the first node;

a second pull-up part configured to output the clock signal as the N-th gate output signal in response to the signal applied to the first node;

a carry part configured to output the clock signal as an N-th carry signal in response to the signal applied to the first node;

a first pull-down part configured to pull down the signal at the first node to a second gate-off voltage in response to a first next carry signal, which is a carry signal of one of next stages;

a second pull-down part configured to pull down the N-th gate output signal to a first gate-off voltage in response to the first next carry signal; and

an inverting part configured to generate an inverting signal based on the clock signal, and based on the first gate-off voltage or the second gate-off voltage, to output the inverting signal to an inverting node,

wherein one of the first pull-up part and the second pull-up part is selectively activated, and

wherein N is a positive integer.

2. The gate driving circuit of claim 1, wherein the gate driving circuit comprises a plurality of stages, and

wherein a gate output voltage of at least one of the stages is fed back.

3. The gate driving circuit of claim 1, wherein the first pull-up part comprises a first pull-up transistor comprising a control electrode coupled to a second node, an input electrode for receiving the clock signal, and an output electrode coupled to a gate output terminal configured to output the N-th gate output signal.

4. The gate driving circuit of claim 3, wherein the second pull-up part comprises a second pull-up transistor comprising a control electrode coupled to a third node, an input electrode for receiving the clock signal, and an output electrode coupled to the gate output terminal configured to output the N-th gate output signal.

5. The gate driving circuit of claim 4, further comprising a first selecting transistor comprising a control electrode for receiving a first selecting signal, an input electrode coupled to the first node, and an output electrode coupled to the second node.

6. The gate driving circuit of claim 5, further comprising a second selecting transistor comprising a control electrode for receiving a second selecting signal, an input electrode coupled to the first node, and an output electrode coupled to the third node.

7. The gate driving circuit of claim 1, further comprising a carry pull-down part configured to pull down the N-th carry signal to the second gate-off voltage in response to the first next carry signal.

8. The gate driving circuit of claim 7, further comprising a first holding part configured to pull down the N-th gate output signal to the first gate-off voltage in response to the inverting signal.

9. The gate driving circuit of claim 8, further comprising a second holding part configured to pull down the first node to the second gate-off voltage in response to the inverting signal.

10. The gate driving circuit of claim 9, further comprising a third holding part configured to pull down the inverting node to the second gate-off voltage in response to the first previous carry signal.

11. The gate driving circuit of claim 10, further comprising a fourth holding part configured to pull down the first node to the second gate-off voltage in response to a second next carry signal, which is a carry signal of one of the next stages and is different from the first next carry signal.

12. The gate driving circuit of claim 11, further comprising a fifth holding part configured to pull down the N-th carry signal to the second gate-off voltage in response to the inverting signal.

13. A display apparatus comprising:

a display panel configured to display an image;

a data driving circuit configured to output a data voltage to the display panel;

a gate driving circuit configured to output a gate output signal to the display panel; and

a gate signal determiner configured to control operation of the gate driving circuit,

wherein the gate driving circuit comprises;

a pull-up control part configured to apply a first previous carry signal, which is a carry signal of one of previous stages, to a first node in response to the first previous carry signal;

a first pull-up part configured to output a clock signal as an N-th gate output signal in response to a signal applied to the first node;

a second pull-up part configured to output the clock signal as the N-th gate output signal in response to the signal applied to the first node;

a carry part configured to output the clock signal as an N-th carry signal in response to the signal applied to the first node;

a first pull-down part configured to pull down the signal at the first node to a second gate-off voltage in response to a first next carry signal, which is a carry signal of one of next stages;

a second pull-down part configured to pull down the N-th gate output signal to a first gate-off voltage in response to the first next carry signal; and

an inverting part configured to generate an inverting signal based on the clock signal, and based on the first gate-off voltage or the second gate-off voltage, to output the inverting signal to an inverting node,

wherein the gate signal determiner is configured to output a selecting signal, which is for activating one of the first pull-up part and the second pull-up part, to the gate driving circuit, and

wherein N is a positive integer.

14. The display apparatus of claim 13, further comprising a power voltage generator configured to output a driving voltage to the gate driving circuit, and comprising the gate signal determiner.

15. The display apparatus of claim 13, further comprising a driving controller configured to control driving timings of the data driving circuit and the gate driving circuit, and comprising the gate signal determiner.

16. The display apparatus of claim 13, wherein the gate driving circuit comprises a plurality of stages, and

wherein a gate output voltage of at least one of the stages is fed back to the gate signal determiner.

17. The display apparatus of claim 13, wherein the first pull-up part comprises a first pull-up transistor comprising a control electrode coupled to a second node, an input electrode for receiving the clock signal, and an output electrode coupled to a gate output terminal configured to output the N-th gate output signal.

18. The display apparatus of claim 17, wherein the second pull-up part comprises a second pull-up transistor comprising a control electrode coupled to a third node, an input electrode for receiving the clock signal, and an output electrode coupled to the gate output terminal configured to output the N-th gate output signal.

19. The display apparatus of claim 18, wherein the gate driving circuit further comprises a first selecting transistor comprising a control electrode for receiving a first selecting signal, an input electrode coupled to the first node, and an output electrode coupled to the second node.

20. The display apparatus of claim 19, wherein the gate driving circuit further comprises a second selecting transistor comprising a control electrode for receiving a second selecting signal, an input electrode coupled to the first node, and an output electrode coupled to the third node.