Memory system and operating method thereof managing counting values for system operations

• US 10,671,297 B2
• Filed: 01/05/2018
• Issued: 06/02/2020
• Est. Priority Date: 05/16/2017
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Park, Chang-Hyun
• Primary Examiner(s): Choi, Charles J
• Application Number:
  US15/862,770
• Publication Number:
  US 20180335959A1
• Time in Patent Office: 879 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A memory system may include: a nonvolatile memory device comprising K memory blocks; and a controller suitable for controlling an operation of the nonvolatile memory device. The controller may include: a counting management unit suitable for using K count codes capable of counting a preset range from a base value to a limit value in order to manage K counting values corresponding to predetermined operations of the K memory blocks, respectively, and adjusting the absolute values of the base value and the limit value using the count code in the form of a 1/N-chain depending on a distribution of the K counting values; and a wear-leveling operation unit suitable for performing a wear-leveling operation on the K memory blocks such that the K counting values are distributed in a section of values corresponding to 1/N of the preset range, the count code may be a J-based number, each of J and K may be a natural number larger than 2, and N may be any one of powers of J larger than 1.

Claims

1. A memory system comprising:

a nonvolatile memory device comprising K memory blocks; and

a controller suitable for controlling an operation of the nonvolatile memory device,

wherein the controller comprises;

a processor suitable for using K count codes, each having an N-bit size, and representing numbers of times select operations are performed on the K memory blocks respectively, wherein the K count codes manage K counting values representing added numbers of the select operations performed on the K memory blocks, respectively, each of the K counting values having a set range defined by a base value and a limit value, which are different for each of the K counting values, and the set range for each counting value overlapping the set range of at least one other counting value of the K counting values, and adjusting the base value and the limit value of a select counting value by using the corresponding count code in the form of a (N−

1)-bit chain depending on a distribution of the K counting values; and

wherein the controller is suitable for performing a wear-leveling operation on the K memory blocks such that the K counting values are distributed in one between lower and upper halves of the set range,

wherein the processor resets a base code and a lower half code during a booting period, such that a join code corresponding to the minimum value of the K counting values, which are checked by joining the K count codes and the base code corresponding to the base value, is equal to or larger than the base code, and becomes smaller than the lower half code larger than the base code by a half value of the count code,

wherein K is a natural number greater than 2, and N is a value of 2 to the power of T, where T is an integer equal to or greater than 1.

2. The memory system of claim 1, wherein the processor resets a code to a limit code corresponding to the limit value, the code being obtained by adding a range code corresponding to the set range to the base code reset during the booting period and subtracting 1 from the added value.

3. The memory system of claim 2, wherein the controller performs a first wear-leveling operation on the K memory blocks such that a join code corresponding to the maximum value of the K counting values becomes smaller than the lower half code, during a wear-leveling period after the booting period.

4. The memory system of claim 3, wherein when it is determined that the join code corresponding to the maximum value of the K counting values is equal to or larger than the lower half code after the first wear-leveling operation was performed during the wear-leveling period, the controller performs a second wear-leveling operation on the K memory blocks, such that the join code corresponding to the minimum value of the K counting values becomes equal to or larger than the lower half code, and the join code corresponding to the maximum value of the K counting values becomes smaller than an upper half code larger by a half value of the count code than the lower half code.

5. The memory system of claim 4, wherein when it is determined that the join code corresponding to the minimum value of the K counting values is equal to or larger than the lower half code after the controller performed the second wear-leveling operation during the wear-leveling period,

the processor resets the lower half code to the base code, resets a code to the limit code, the code being obtained by adding the range code to the base code reset during the wear-leveling period and subtracting 1 from the added value, resets a code to the lower half code, the code being larger by a half value of the count code than the base code reset during the wear-leveling period, and resets a code to the upper half code, the code being larger by a half value of the count code than the lower half code reset during the wear-leveling period.

6. The memory system of claim 5, wherein the controller reads the base code from a select memory block among the K memory blocks during the booting period, and

when the base code is reset through the operation of the processor during the booting period or the wear-leveling period, the controller stores the reset base code in the select memory block.

7. The memory system of claim 6, wherein the controller further comprises a memory,

wherein the controller reads the K count codes from the respective K memory blocks or the select memory block during the booting period or the wear-leveling period, and controls the memory to manage the read count codes,

wherein when a count code among the K count codes is updated by one of the select operations after the booting period, the controller stores the updated count code in the corresponding memory blocks or the select memory block at a specific point of time.

8. The memory system of claim 5,

wherein each of the base code, the join code, the lower half code, the upper half code and the limit code has the N-bit or greater size, and

the range code has (N+1)-bit size and a greater value than the maximum value of the count code by a value of 1.

9. The memory system of claim 8, wherein the processor generates the join codes corresponding to the K counting values by adding the K count codes to the base code, respectively, during the booting period or the wear-leveling period.

10. An operating method of a memory system which includes a nonvolatile memory device having K memory blocks, the operating method comprising:

managing K counting values representing added numbers of select operations performed on the K memory blocks by using K count codes, each having an N-bit size and representing numbers of times the select operations are performed on the K memory blocks, respectively, each of the K counting values having a set range defined by a base value and a limit value, which are different for each of the K counting values, and the set range for each counting value overlapping the set range of at least one other counting value of the K counting values;

adjusting the base value and the limit value of a select counting value by using the corresponding count code in the form of a (N−

1)-bit chain depending on a distribution of the K counting values managed by the managing of the K counting values; and

performing a wear-leveling operation on the K memory blocks such that the K counting values managed by the managing of the K counting values are distributed in one between lower and upper halves of the set range,

wherein the adjusting of the values comprises;

checking, in a first check step, the K counting values by joining the K count codes and a base code corresponding to the base value during a booting period; and

resetting, in a first reset step, the base code and a lower half code such that a join code corresponding to the minimum value of the K counting values checked in the first check step is equal to or larger than the base code, and becomes smaller than the lower half code larger than the base code by a half value of the count code,

wherein K is a natural number greater than 2, and N is a value of 2 to the power of T, where T is an integer equal to or greater than 1.

11. The operating method of claim 10, wherein the adjusting of the values further comprises resetting, in a second reset step, a code to a limit code corresponding to the limit value, the code being obtained by adding a range code corresponding to the set range to the base code reset in the first reset step and subtracting 1 from the added value.

12. The operating method of claim 11, wherein the performing of the wear-leveling operation comprises:

checking, in a second check step, the K counting values by joining the K count codes and the base code corresponding to the base value during a wear-leveling period after the booting period; and

performing, in a first leveling step, a wear-leveling operation on the K memory blocks such that a join code corresponding to the maximum value of the K counting values checked in the second check step becomes smaller than the lower half code.

13. The operating method of claim 12, wherein the performing of the wear-leveling operation further comprises performing, in a second leveling step, a wear-leveling operation on the K memory blocks such that the join code corresponding to the minimum value of the K counting values checked through the second check step becomes equal to or larger than the lower half code, and the join code corresponding to the maximum value of the K counting values becomes smaller than an upper half code larger by a half value of the count code than the lower half code, when it is determined that the join code corresponding to the maximum value of the K counting values checked through the second check step is equal to or larger than the lower half code, after the first wear-leveling operation.

14. The operating method of claim 13, wherein the adjusting of the values comprises:

checking, in a third check step, the K counting values by joining the K count codes and the base code corresponding to the base value, after the second leveling step; and

resetting, in a third reset step, the lower half code to the base code, resetting a code to the limit code, the code being obtained by adding the range code to the base code reset during the wear-leveling period and subtracting 1 from the added value, resetting a code to the lower half code, the code being larger by a half value of the count code than the base code reset during the wear-leveling period, and resetting a code to the upper half code, the code being larger by a half value of the count code than the lower half code reset during the wear-leveling period, when it is determined that the join code corresponding to the minimum value of the K counting values checked through the third check step is equal to or larger than the lower half code.

15. The operating method of claim 14, further comprising:

reading the base code from a select memory block of the K memory blocks during the booting period; and

storing the base code reset during the booting period or the wear-leveling period into the select memory block, in case where the base code is reset.

16. The operating method of claim 15, wherein the memory system further includes a memory,

wherein the operating method further comprises:

reading the K count codes from the respective K memory blocks or the select memory block during the booting period or the wear-leveling period, and controlling the memory to manage the read count codes, and

storing a count code among the K count codes into the corresponding memory blocks or the select memory block at a specific point of time, when the count code is updated through one of the select operations after the booting period.

17. The operating method of claim 14,

wherein each of the base code, the join code, the lower half code, the upper half code and the limit code has the N-bit or greater size, and

the range code has (N+1)-bit size and a greater value than the maximum value of the count code by a value of 1.

18. The operating method of claim 17, wherein each of the first to third check steps comprises generating the join codes corresponding to the K counting values by adding the K count codes to the base code, respectively.