Memory system

• US 10,671,523 B2
• Filed: 10/19/2017
• Issued: 06/02/2020
• Est. Priority Date: 03/17/2017
• Status: Active Grant

• Current Assignee: MIMIRIP LLC (Ideahub, Inc.)
• Original Assignee: SK Hynix Inc.
• Inventors: Jung, Byung-Soo
• Primary Examiner(s): Rossiter, Sean D
• Assistant Examiner(s): Wu, Stephanie
• Application Number:
  US15/787,821
• Publication Number:
  US 20180267895A1
• Time in Patent Office: 957 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A memory system include: a plurality of first memory devices each coupled to a first channel and including a plurality of first memory blocks; a plurality of second memory devices each coupled to a second channel and including a plurality of second memory blocks; a first access controller suitable for controlling an access to the first memory blocks; a second access controller suitable for controlling an access to the second memory blocks; and a bad block controller suitable for: selecting one between the first and second access controllers by comparing bad physical addresses corresponding to bad blocks included in each of the first and second memory devices with first and second physical addresses respectively corresponding to the first and second memory blocks, and transferring one of the first and second physical addresses and substitute physical address that replace the bad physical addresses.

Claims

1. A memory system, comprising:

a plurality of first memory devices each coupled to a first way of a first channel and including a plurality of first memory blocks;

a plurality of second memory devices each coupled to a second way of the first channel and including a plurality of second memory blocks;

a plurality of third memory devices each coupled to a first way of a second channel and including a plurality of third memory blocks;

a plurality of fourth memory devices each coupled to a second way of the second channel and including a plurality of fourth memory blocks;

a first access controller suitable for controlling an access to the first memory blocks;

a second access controller suitable for controlling an access to the second memory blocks;

a third access controller suitable for controlling an access to the third memory blocks;

a fourth access controller suitable for controlling an access to the fourth memory blocks;

a first channel controller suitable for controlling an access to the first and second access controllers;

a second channel controller suitable for controlling an access to the third and fourth access controllers;

a first bad block controller suitable for;

comparing an inputted first physical address indicating a location in the plurality of first memory devices with first channel bad physical addresses indicating the bad blocks coupled via the first channel;

outputting a second substitute physical address replaced with the inputted first physical address when the inputted first physical address is included in second bad physical addresses among the first channel bad physical addresses, wherein the second substitute physical address indicates a location in the plurality of second memory devices;

comparing an inputted second physical address indicating a location in the plurality of second memory devices with first channel bad physical addresses indicating the bad blocks coupled via the first channel; and

outputting a first substitute physical address replaced with the inputted second physical address when the inputted second physical address is included in first bad physical addresses among the first channel bad physical addresses, wherein the first substitute physical address indicates a location in the plurality of first memory devices, and

a second bad block controller suitable for;

comparing an inputted third physical address indicating a location in the plurality of third memory devices with second channel bad physical addresses indicating the bad blocks coupled via the second channel;

outputting a fourth substitute physical address replaced with the inputted third physical address when the inputted third physical address is included in fourth bad physical addresses among the second channel bad physical addresses, wherein the fourth substitute physical address indicates a location in the plurality of fourth memory devices;

comparing an inputted fourth physical address indicating a location in the plurality of fourth memory devices with second channel bad physical addresses indicating the bad blocks coupled via the second channel; and

outputting a third substitute physical address replaced with the inputted fourth physical address when the inputted fourth physical address is included in third bad physical addresses among the second channel bad physical addresses, wherein the third substitute physical address indicates a location in the plurality of third memory devices,

wherein the first bad block controller includes;

a first bad block table including mapping relation information between partial entries of the first bad physical addresses with the first substitute physical address;

a second bad block table including mapping relation information between the second bad physical addresses with the second substitute physical address; and

a first bad information loading element suitable for;

loading information of the first channel bad physical addresses and the first and second substitute physical addresses from the first and second memory devices,

deciding which of the first and second substitute physical addresses are to be mapped to the first channel bad physical addresses based on the number of the loaded first channel bad physical addresses, and

generating the first and second bad block tables.

2. The memory system of claim 1, wherein the first bad block controller further includes:

a first path control element suitable for;

selecting the first channel controller and the first access controller and transferring the first substitute physical address when the inputted second physical address is identical to the first bad physical addresses,

selecting the first channel controller and the second access controller and transferring the second substitute physical address when the inputted first physical address is identical to the second bad physical addresses, and

selecting the first channel controller and the first access controller and transferring the inputted first physical address or selecting the first channel controller and the second access controller and transferring the second inputted physical addresses when the first and second physical address are not identical to the first channel bad physical addresses.

3. The memory system of claim 2, wherein the second bad block controller includes:

a third bad block table including mapping relation information between the third bad physical addresses with the third substitute physical address;

a fourth bad block table including mapping relation information between the fourth bad physical addresses with the fourth substitute physical address; and

a second path control element suitable for;

selecting the second channel controller and the third access controller and transferring the third substitute physical address when the inputted fourth physical address is identical to the third bad physical addresses,

selecting the second channel controller and the fourth access controller and transferring the fourth substitute physical address when the inputted third physical address is identical to the fourth bad physical addresses, and

selecting the second channel controller and the third access controller and transferring the inputted third physical address or selecting the second channel controller and the fourth access controller and transferring the inputted fourth physical address when the inputted third and fourth physical addresses are not identical to the second channel bad physical addresses.

4. The memory system of claim 3, wherein the first path control element includes:

a first specific path control element suitable for;

selecting the first channel controller and the second access controller and transferring the second substitute physical address when the inputted first physical address is identical to the second bad physical addresses, and

selecting the first channel controller and the first access controller and transferring the inputted first physical addresses when the inputted first physical address is not identical to the first channel bad physical addresses; and

a second specific path control element suitable for;

selecting the first channel controller and the first access controller and transferring the first substitute physical address when the inputted second physical address is identical to the first bad physical addresses; and

selecting the first channel controller and the second access controller and transferring the inputted second physical addresses when the inputted second physical address is not identical to the first channel bad physical addresses.

5. The memory system of claim 4, wherein the second path control element includes:

a third specific path control element suitable for;

selecting the second channel controller and the fourth access controller and transferring the fourth substitute physical address when the inputted third physical address is identical to the fourth bad physical addresses, and

selecting the second channel controller and the third access controller and transferring the inputted third physical addresses when the inputted third physical address is not identical to the second channel bad physical addresses; and

a fourth specific path control element suitable for;

selecting the second channel controller and the third access controller and transferring the third substitute physical address when the inputted fourth physical address is identical to the third bad physical addresses; and

selecting the second channel controller and the fourth access controller and transferring the inputted fourth physical address when the inputted fourth physical address is not identical to the second channel bad physical addresses.

6. The memory system of claim 3, wherein the first bad information loading element generates the first and second bad block tables by checking out the total number of the first channel bad physical addresses that are stored in the first and second memory devices, and distributes the first channel bad physical addresses in such a manner that the number of the first bad physical addresses and the number of the second bad physical addresses do not exceed a predetermined number of difference.

7. The memory system of claim 3, wherein the second bad block controller further includes a second bad information loading element suitable for:

loading information of the second channel bad physical addresses and the third and fourth substitute physical addresses that are stored in the third and fourth memory devices,

deciding which of the third and fourth substitute physical addresses are to be mapped to the second channel bad physical addresses based on the number of the loaded second channel bad physical addresses, and

generating the third and fourth bad block tables.

8. The memory system of claim 7, wherein the second bad information loading element generates the third and fourth bad block tables by checking out the total number of the second channel bad physical addresses that are stored in the third and fourth memory devices, and distributes the second channel bad physical addresses in such a manner that the number of the third bad physical addresses and the number of the fourth bad physical addresses do not exceed a predetermined number of difference.

9. A memory system, comprising:

a plurality of first memory devices each coupled to a first way of a first channel and including a plurality of first memory blocks;

a plurality of second memory devices each coupled to a second way of the first channel and including a plurality of second memory blocks;

a plurality of third memory devices each coupled to a first way of a second channel and including a plurality of third memory blocks;

a plurality of fourth memory devices each coupled to a second way of the second channel and including a plurality of fourth memory blocks;

a first access controller suitable for controlling an access to the first memory blocks;

a second access controller suitable for controlling an access to the second memory blocks;

a third access controller suitable for controlling an access to the third memory blocks;

a fourth access controller suitable for controlling an access to the fourth memory blocks;

a first channel controller suitable for controlling an access to the first and second access controllers;

a second channel controller suitable for controlling an access to the third and fourth access controllers;

a bad block controller suitable for;

comparing an each of inputted first to fourth physical addresses indicating a location in each of first to fourth memory devices with bad physical addresses indicating the bad blocks coupled via the first and second channel;

outputting an each of second to fourth substitute physical addresses replaced with the inputted first physical address when the inputted first physical address is included in each of second to fourth bad physical addresses among the bad physical addresses, wherein the each of second to fourth substitute physical addresses indicates a location in the each of second to fourth memory devices;

outputting an each of first and third to fourth substitute physical addresses replaced with the inputted second physical address when the inputted second physical address is included in each of first and third to fourth bad physical addresses among the bad physical addresses, wherein the each of first and third to fourth substitute physical addresses indicates a location in the each of first and third to fourth memory devices;

outputting an each of first to second and fourth substitute physical addresses replaced with the inputted third physical address when the inputted third physical address is included in each of first to second and fourth bad physical addresses among the bad physical addresses, wherein the each of first to second and fourth substitute physical addresses indicates a location in the each of first to second and fourth memory devices; and

outputting an each of first to third substitute physical addresses replaced with the inputted fourth physical address when the inputted fourth physical address is included in each of first to third bad physical addresses among the bad physical addresses, wherein the each of first to third substitute physical addresses indicates a location in the each of first to third memory devices,

wherein the bad block controller includes;

a first bad block table including mapping relation information between the first bad physical addresses with the first substitute physical address;

a second bad block table including mapping relation information between the second bad physical addresses with the second substitute physical address;

a third bad block table including mapping relation information between the third bad physical addresses with the third substitute physical address;

a fourth bad block table including mapping relation information between the fourth bad physical addresses with the fourth substitute physical address; and

a bad information loading element suitable for;

loading information of the bad physical addresses and the first to fourth substitute physical addresses from the first to fourth memory devices,

deciding which of the first to fourth substitute physical addresses are to be mapped to the bad physical addresses based on the number of the loaded bad physical addresses, and

generating the first to fourth bad block tables.

10. The memory system of claim 9, wherein the bad block controller further includes:

a path control element suitable for;

selecting the first channel controller and the first access controller and transferring the first substitute physical address when the each of inputted second to fourth physical address is identical to the first bad physical addresses;

selecting the first channel controller and the second access controller and transferring the second substitute physical address when the each of inputted first and third to fourth physical address is identical to the second bad physical addresses;

selecting the second channel controller and the third access controller and transferring the third substitute physical address when the each of inputted first to second and fourth physical address is identical to the third bad physical addresses;

selecting the second channel controller and the fourth access controller and transferring the fourth substitute physical address when the each of inputted first to third physical address is identical to the fourth bad physical addresses; and

selecting the first channel controller and the first access controller and transferring the inputted first physical address, or selecting the first channel controller and the second access controller and transferring the inputted second physical address, or selecting the second channel controller and the third access controller and transferring the inputted third physical address, or selecting the second channel controller and the fourth access controller and transferring the inputted fourth physical address when the each of inputted first to fourth physical address is not identical to the bad physical addresses.

11. The memory system of claim 10, wherein the path control element includes:

a first specific path control element suitable for;

selecting the first channel controller and the second access controller and transferring the second substitute physical address when the inputted first physical address is identical to the second bad physical addresses,

selecting the second channel controller and the third access controller and transferring the third substitute physical address when the inputted first physical address is identical to the third bad physical addresses,

selecting the second channel controller and the fourth access controller and transferring the fourth substitute physical address when the inputted first physical address is identical to the fourth bad physical addresses, and

selecting the first channel controller and the first access controller and transferring the inputted first physical address when the inputted first physical address is not identical to the bad physical addresses;

a second specific path control element suitable for;

selecting the first channel controller and the first access controller and transferring the first substitute physical address when the inputted second physical address is identical to the first bad physical addresses,

selecting the second channel controller and the third access controller and transferring the third substitute physical address when the inputted second physical address is identical to the third bad physical addresses,

selecting the second channel controller and the fourth access controller and transferring the fourth substitute physical address when the inputted second physical address is identical to the fourth bad physical addresses, and

selecting the first channel controller and the second access controller and transferring the inputted second physical address when the inputted second physical address is not identical to the bad physical addresses;

a third specific path control element suitable for;

selecting the first channel controller and the first access controller and transferring the first substitute physical address when the inputted third physical address is identical to the first bad physical addresses,

selecting the first channel controller and the second access controller and transferring the second substitute physical address when the inputted third physical address is identical to the second bad physical addresses,

selecting the second channel controller and the fourth access controller and transferring the fourth substitute physical address when the inputted third physical address is identical to the fourth bad physical addresses, and

selecting the second channel controller and the third access controller and transferring the inputted third physical address when the inputted third physical address is not identical to the bad physical addresses; and

a fourth specific path control element suitable for;

selecting the first channel controller and the first access controller and transferring the first substitute physical address when the inputted fourth physical address is identical to the first bad physical addresses,

selecting the first channel controller and the second access controller and transferring the second substitute physical address when the inputted fourth physical address is identical to the second bad physical addresses,

selecting the second channel controller and the third access controller and transferring the third substitute physical address when the inputted fourth physical address is identical to the third bad physical addresses, and

selecting the second channel controller and the fourth access controller and transferring the inputted fourth physical address when the inputted fourth physical address is not identical to the bad physical addresses.

12. The memory system of claim 10, wherein the bad information loading element generates the first to fourth bad block tables by checking out the total number of the bad physical addresses that are stored in the first to fourth memory devices, and distributes the bad physical addresses in such a manner that the number of the first bad physical addresses, the number of the second bad physical addresses, the number of the third bad physical addresses, and the number of the fourth bad physical addresses do not exceed a predetermined number of difference.