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Memory system

  • US 10,671,523 B2
  • Filed: 10/19/2017
  • Issued: 06/02/2020
  • Est. Priority Date: 03/17/2017
  • Status: Active Grant
First Claim
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1. A memory system, comprising:

  • a plurality of first memory devices each coupled to a first way of a first channel and including a plurality of first memory blocks;

    a plurality of second memory devices each coupled to a second way of the first channel and including a plurality of second memory blocks;

    a plurality of third memory devices each coupled to a first way of a second channel and including a plurality of third memory blocks;

    a plurality of fourth memory devices each coupled to a second way of the second channel and including a plurality of fourth memory blocks;

    a first access controller suitable for controlling an access to the first memory blocks;

    a second access controller suitable for controlling an access to the second memory blocks;

    a third access controller suitable for controlling an access to the third memory blocks;

    a fourth access controller suitable for controlling an access to the fourth memory blocks;

    a first channel controller suitable for controlling an access to the first and second access controllers;

    a second channel controller suitable for controlling an access to the third and fourth access controllers;

    a first bad block controller suitable for;

    comparing an inputted first physical address indicating a location in the plurality of first memory devices with first channel bad physical addresses indicating the bad blocks coupled via the first channel;

    outputting a second substitute physical address replaced with the inputted first physical address when the inputted first physical address is included in second bad physical addresses among the first channel bad physical addresses, wherein the second substitute physical address indicates a location in the plurality of second memory devices;

    comparing an inputted second physical address indicating a location in the plurality of second memory devices with first channel bad physical addresses indicating the bad blocks coupled via the first channel; and

    outputting a first substitute physical address replaced with the inputted second physical address when the inputted second physical address is included in first bad physical addresses among the first channel bad physical addresses, wherein the first substitute physical address indicates a location in the plurality of first memory devices, anda second bad block controller suitable for;

    comparing an inputted third physical address indicating a location in the plurality of third memory devices with second channel bad physical addresses indicating the bad blocks coupled via the second channel;

    outputting a fourth substitute physical address replaced with the inputted third physical address when the inputted third physical address is included in fourth bad physical addresses among the second channel bad physical addresses, wherein the fourth substitute physical address indicates a location in the plurality of fourth memory devices;

    comparing an inputted fourth physical address indicating a location in the plurality of fourth memory devices with second channel bad physical addresses indicating the bad blocks coupled via the second channel; and

    outputting a third substitute physical address replaced with the inputted fourth physical address when the inputted fourth physical address is included in third bad physical addresses among the second channel bad physical addresses, wherein the third substitute physical address indicates a location in the plurality of third memory devices,wherein the first bad block controller includes;

    a first bad block table including mapping relation information between partial entries of the first bad physical addresses with the first substitute physical address;

    a second bad block table including mapping relation information between the second bad physical addresses with the second substitute physical address; and

    a first bad information loading element suitable for;

    loading information of the first channel bad physical addresses and the first and second substitute physical addresses from the first and second memory devices,deciding which of the first and second substitute physical addresses are to be mapped to the first channel bad physical addresses based on the number of the loaded first channel bad physical addresses, andgenerating the first and second bad block tables.

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