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Architecture for ordered write of data collected in parallel

  • US 10,671,782 B2
  • Filed: 10/29/2018
  • Issued: 06/02/2020
  • Est. Priority Date: 10/29/2018
  • Status: Active Grant
First Claim
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1. A computer-implemented method of performing an ordered write of timing analysis data obtained in parallel during integrated circuit development, the method comprising:

  • processing two or more data sets with two or more processors in parallel, wherein the two or more data sets result from timing analysis and correspond with two or more paths in an integrated circuit, each path includes a set of interconnected components, and the processing includes collecting and formatting information from each of the two or more data sets to obtain the timing analysis data associated with each of the two or more paths;

    determining a next timing analysis data among the timing analysis data obtained by the processing using an ordered list of the two or more data sets that correspond with the timing analysis data;

    consulting an availability vector indicating availability of the timing analysis data associated with each of the two or more data sets to determine whether the next timing analysis data is available; and

    writing the next timing analysis data as soon as it is available according to the availability vector prior to completion of the processing of others of the two or more data sets.

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