Architecture for ordered write of data collected in parallel

• US 10,671,782 B2
• Filed: 10/29/2018
• Issued: 06/02/2020
• Est. Priority Date: 10/29/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kumar, Maurya Prabhat, Raghunathan, SheshaShayee K
• Primary Examiner(s): Memula, Suresh
• Application Number:
  US16/173,344
• Publication Number:
  US 20200134115A1
• Time in Patent Office: 582 Days
• Field of Search: 716113
• CPC Class Codes: G06F 16/1858 Parallel file systems, i.e. file systems supporting multiple processors
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A system and method to perform an ordered write of timing analysis data obtained in parallel during integrated circuit development process two or more data sets with two or more processors in parallel. The two or more data sets result from timing analysis and correspond with two or more paths, each path includes a set of interconnected components, and the processing includes collecting and formatting information to obtain the timing analysis data associated with each of the two or more paths. The method includes determining a next timing analysis data using an ordered list of the two or more data sets that correspond with the timing analysis data, consulting an availability vector to determine whether the next timing analysis data is available, and writing the next timing analysis data as soon as it is available prior to completion of the processing of others of the two or more data sets.

Claims

1. A computer-implemented method of performing an ordered write of timing analysis data obtained in parallel during integrated circuit development, the method comprising:

processing two or more data sets with two or more processors in parallel, wherein the two or more data sets result from timing analysis and correspond with two or more paths in an integrated circuit, each path includes a set of interconnected components, and the processing includes collecting and formatting information from each of the two or more data sets to obtain the timing analysis data associated with each of the two or more paths;

determining a next timing analysis data among the timing analysis data obtained by the processing using an ordered list of the two or more data sets that correspond with the timing analysis data;

consulting an availability vector indicating availability of the timing analysis data associated with each of the two or more data sets to determine whether the next timing analysis data is available; and

writing the next timing analysis data as soon as it is available according to the availability vector prior to completion of the processing of others of the two or more data sets.

2. The computer-implemented method according to claim 1, further comprising assigning a number of the two or more data sets to each of the two or more processors based on the number being a predefined workgroup size.

3. The computer-implemented method according to claim 2, further comprising changing the predefined workgroup size.

4. The computer-implemented method according to claim 1, further comprising updating the availability vector following completion of the processing of any of the two or more data sets, wherein the availability vector includes an entry associated with each of the two or more data sets.

5. The computer-implemented method according to claim 1, further comprising maintaining a write status vector with an entry associated with each of the two or more data sets, wherein the write status vector is updated as each corresponding timing analysis data is prepared for the writing and as the writing is completed.

6. The computer-implemented method according to claim 1, wherein the collecting and formatting information from each of the two or more data sets to obtain the timing analysis data includes obtaining timing data at an input pin and output pin of each component among the set of interconnected components of the corresponding path among the two or more paths.

7. The computer-implemented method according to claim 1, further comprising providing a final integrated circuit design for fabrication following the timing analysis.

8. A system to perform an ordered write of timing analysis data obtained in parallel during integrated circuit development, the system comprising:

a memory device configured to store two or more data sets resulting from timing analysis of an integrated circuit and corresponding with two or more paths in the integrated circuit, each path including a set of interconnected components;

two or more processors configured to process the two or more data sets in parallel, wherein the processing includes collecting and formatting information from each of the two or more data sets to obtain the timing analysis data associated with each of the two or more paths; and

a write processor configured to determine a next timing analysis data among the timing analysis data obtained by the processing using an ordered list of the two or more data sets that correspond with the timing analysis data, to determine whether the next timing analysis data is available by consulting an availability vector indicating availability of the timing analysis data associated with each of the two or more data sets, and to write the next timing analysis data as soon as it is available according to the availability vector prior to completion of the processing of others of the two or more data sets.

9. The system according to claim 8, wherein each of the two or more processors is assigned a number of the two or more data sets to each of the two or more processors based on the number being a predefined workgroup size.

10. The system according to claim 8, wherein one of the two or more processors updates the availability vector following completion of processing of any of the two or more data sets, wherein the availability vector includes an entry associated with each of the two or more data sets.

11. The system according to claim 8, wherein the write processor maintains a write status vector with an entry associated with each of the two or more data sets and is further configured to update the write status vector as each corresponding timing analysis data is written.

12. The system according to claim 8, wherein the timing analysis data includes timing data at an input pin and output pin of each component among the set of interconnected components of the corresponding path among the two or more paths.

13. The system according to claim 8, wherein a final integrated circuit design is provided for fabrication following the timing analysis.

14. A computer program product for performing an ordered write of timing analysis data obtained in parallel during integrated circuit development, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to perform a method comprising:

processing two or more data sets with two or more processors in parallel, wherein the two or more data sets result from timing analysis of an integrated circuit and correspond with two or more paths in the integrated circuit, each path includes a set of interconnected components, and the processing includes collecting and formatting information from each of the two or more data sets to obtain the timing analysis data associated with each of the two or more paths;

determining a next timing analysis data among the timing analysis data obtained by the processing using an ordered list of the two or more data sets that correspond with the timing analysis data;

consulting an availability vector indicating availability of the timing analysis data associated with each of the two or more data sets to determine whether the next timing analysis data is available; and

writing the next timing analysis data as soon as it is available according to the availability vector prior to completion of the processing of others of the two or more data sets.

15. The computer program product according to claim 14, further comprising assigning a number of the two or more data sets to each of the two or more processors based on the number being a predefined workgroup size.

16. The computer program product according to claim 15, further comprising changing the predefined workgroup size.

17. The computer program product according to claim 14, further comprising updating the availability vector following completion of the processing of any of the two or more data sets, wherein the availability vector includes an entry associated with each of the two or more data sets.

18. The computer program product according to claim 14, further comprising maintaining a write status vector with an entry associated with each of the two or more data sets, wherein the write status vector is updated as each corresponding timing analysis data is prepared for the writing and as the writing is completed.

19. The computer program product according to claim 14, wherein the collecting and formatting information from each of the two or more data sets to obtain the timing analysis data includes obtaining timing data at an input pin and output pin of each component among the set of interconnected components of the corresponding path among the two or more paths.

20. The computer program product according to claim 14, further comprising providing a final integrated circuit design for fabrication following the timing analysis.