Analog neuromorphic circuit implemented using resistive memories
First Claim
1. An analog neuromorphic circuit that implements a plurality of resistive memories, comprising:
- a plurality of input voltages applied to a plurality of inputs of the analog neuromorphic circuit with each input voltage applied to a corresponding horizontal wire from a plurality of horizontal wires;
a plurality of resistive memories with each resistive memory positioned at an intersection of the corresponding horizontal wire from the plurality of horizontal wires and a corresponding vertical wire from a pair of vertical wires with each horizontal wire interesting a first vertical wire and a second vertical wire from the pair of vertical wires forming a crossbar configuration and configured to;
provide a conductance to each input voltage applied to each of the inputs of each corresponding wire so that each input voltage is multiplied in parallel by the corresponding conductance of each corresponding resistive memory, andgenerate a corresponding current as each conductance of each corresponding resistive memory is applied to each input voltage so that each corresponding current is added in parallel as each corresponding current propagates along the first vertical wire and the second vertical wire simultaneously with each multiplication of each input voltage by each corresponding conductance of each resistive memory;
a comparator coupled to the first vertical wire at a first input and to the second vertical wire at a second input and configured to compare a first voltage value associated with the first accumulative current that is conducted by the first vertical wire and a second voltage value associated with the second accumulative current that is conducted by the second vertical wire, wherein a first conductance of the resistive memories positioned on the first vertical wire and a second conductance of the resistive memories positioned on the second vertical wire are adjusted relative to each other based on the first voltage value and the second voltage value to obtain a functionality of the analog neuromorphic circuit; and
an output signal that is configured to execute the functionality of the analog neuromorphic circuit that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel and the adjusted first conductance and second conductance.
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Abstract
An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.
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Citations
20 Claims
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1. An analog neuromorphic circuit that implements a plurality of resistive memories, comprising:
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a plurality of input voltages applied to a plurality of inputs of the analog neuromorphic circuit with each input voltage applied to a corresponding horizontal wire from a plurality of horizontal wires; a plurality of resistive memories with each resistive memory positioned at an intersection of the corresponding horizontal wire from the plurality of horizontal wires and a corresponding vertical wire from a pair of vertical wires with each horizontal wire interesting a first vertical wire and a second vertical wire from the pair of vertical wires forming a crossbar configuration and configured to; provide a conductance to each input voltage applied to each of the inputs of each corresponding wire so that each input voltage is multiplied in parallel by the corresponding conductance of each corresponding resistive memory, and generate a corresponding current as each conductance of each corresponding resistive memory is applied to each input voltage so that each corresponding current is added in parallel as each corresponding current propagates along the first vertical wire and the second vertical wire simultaneously with each multiplication of each input voltage by each corresponding conductance of each resistive memory; a comparator coupled to the first vertical wire at a first input and to the second vertical wire at a second input and configured to compare a first voltage value associated with the first accumulative current that is conducted by the first vertical wire and a second voltage value associated with the second accumulative current that is conducted by the second vertical wire, wherein a first conductance of the resistive memories positioned on the first vertical wire and a second conductance of the resistive memories positioned on the second vertical wire are adjusted relative to each other based on the first voltage value and the second voltage value to obtain a functionality of the analog neuromorphic circuit; and an output signal that is configured to execute the functionality of the analog neuromorphic circuit that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel and the adjusted first conductance and second conductance. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for generating computation operations in parallel by implementing a plurality of resistive memories, comprising:
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applying a plurality of input voltages to a plurality of inputs of an analog neuromorphic circuit with each input voltage applied to a corresponding horizontal wire from a plurality of horizontal wires; providing, by a plurality of resistive memories, a conductance to each input voltage applied to each of the inputs of each corresponding wire so that each input voltage is multiplied in parallel by the corresponding conductance of each corresponding resistive memory, wherein each resistive memory is positioned at an intersection of the corresponding horizontal wire from the plurality of horizontal wires and a corresponding vertical wire from a pair of vertical wires with each horizontal wire intersecting a first vertical wire and a second vertical wire from the pair of vertical wires forming a crossbar configuration; generating a corresponding current for each input voltage as each conductance of each corresponding resistive memory is applied to each input voltage so that each corresponding current is added in parallel as each corresponding current propagates along the first vertical wire and the second vertical wire simultaneously with each multiplication of each input voltage by each corresponding conductance of each resistive memory; comparing, by a comparator coupled to the first vertical wire at a first input and to the second vertical wire at a second input, a first voltage value associated with the first accumulative current that is conducted by the first vertical wire and a second voltage value associated with the second accumulative current that is conducted by the second vertical wire, wherein a first conductance of the resistive memories positioned on the first vertical wire and a second conductance of the resistive memories positioned on the second vertical wire are adjusted relative to each other based on the first voltage value and the second voltage value to obtain a functionality of the analog neuromorphic circuit; and generating an output signal from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel and the adjusted first conductance and second conductance, wherein the functionality of the analog neuromorphic circuit is executed based on the output signal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification