In-memory convolution for machine learning

• US 10,672,469 B1
• Filed: 11/30/2018
• Issued: 06/02/2020
• Est. Priority Date: 11/30/2018
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lung, Hsiang-Lan
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US16/205,743
• Publication Number:
  US 20200176056A1
• Time in Patent Office: 550 Days
• CPC Class Codes: G06N 20/00 Machine learning
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods

Abstract

A device comprises a first block of memory cells, a second block of memory cells to store a feature array, and a third block of memory cells to store an array of output values. Sensing circuitry is coupled to the first block of memory cells and the second block of memory cells to compare electrical differences between the memory cells in the first block and the memory cells in the second block to generate the array of output values. Writing circuitry is operatively coupled to the third block to store the array of output values in the third block of memory cells.

Claims

1. A device, comprising:

a first block of memory cells;

a second block of memory cells to store a feature array;

a third block of memory cells to store an array of output values at analog levels;

sensing circuitry coupled to the first block of memory cells and the second block of memory cells to compare electrical differences between the memory cells in the first block and the memory cells in the second block to generate the array of output values; and

writing circuitry operatively coupled to the third block to store the array of output values in the third block of memory cells.

2. The device of claim 1, wherein

for a set of frames of cells in the first block, the sensing circuitry is configured to compare electrical differences between the feature array with each frame in the set of frames to generate the array of output values, where each value in the array of output values corresponds to a frame in the set of frames, and indicates electrical differences between analog values from its corresponding frame and analog values from the feature array.

3. The device of claim 2, including address generation circuits that apply addresses for the set of frames and the feature array to the first block and the second block in coordination with the sensing circuitry comparing the electrical differences.

4. The device of claim 1, wherein the first block is configured to store an input array.

5. The device of claim 1, comprising:

a fourth block of memory cells to store a filter array;

a fifth block of memory cells to store an input array;

convolution circuitry operatively coupled to the fourth block of memory cells and the fifth block of memory cells to execute in-place convolution of a function of the filter array over the input array to generate an array of convolved values; and

writing circuitry operatively coupled to the first block of memory cells to store the array of convolved values in the first block.

6. The device of claim 5, wherein

the input array and the filter array include digital values, and the convolution circuitry receives the digital values as inputs to the function;

and

for a set of frames of cells in the input array, the function convolves the filter array with each frame in the set of frames to generate the array of convolved values, where each value in the array of convolved values corresponds to a frame in the set of frames, and indicates a number of digital values from its corresponding frame that matches corresponding digital values from the filter array.

7. The device of claim 6, including address generation circuits that apply addresses for the set of frames in the input array and the filter array to the fifth block and the fourth block in coordination with the in-place convolution.

8. The device of claim 1, wherein the writing circuitry operatively coupled to the third block is configured to store an analog level in each cell of the third block for the array of output values.

9. The device of claim 1, wherein the writing circuitry applies a sequence of write pulses for each cell in the third block having a number of write pulses determined according to a corresponding output value in the array of output values.

10. The device of claim 1, wherein the writing circuitry applies a sequence of write pulses for each cell in the third block having a pulse duration determined according to a corresponding output value in the array of output values.

11. The device of claim 1, wherein the writing circuitry applies a sequence of write pulses for each cell in the third block having a tail length of a write pulse determined according to a corresponding output value in the array of output values.

12. The device of claim 1, wherein the first, second and third blocks of memory cells are implemented on a single integrated circuit or multichip module under one package.

13. A method of operating a device comprising a first block of memory cells, a second block of memory cells to store a feature array, and a third block of memory cells to store an array of output values at analog levels, the method comprising:

comparing electrical differences between memory cells in the first block and the memory cells in the second block to generate the array of output values; and

storing the array of output values in the third block of memory cells.

14. The method of claim 13, comprising:

for a set of frames of cells in the first block, comparing electrical differences between the feature array with each frame in the set of frames to generate the array of output values, where each value in the array of output values corresponds to a frame in the set of frames, and indicates electrical differences between analog values from its corresponding frame and analog values from the feature array.

15. The method of claim 14, comprising:

applying addresses for the set of frames and the feature array to the first block and the second block in coordination with the sensing circuitry comparing the electrical differences.

16. The method of claim 13, comprising:

storing an input array in the first block of memory cells.

17. The method of claim 13, wherein the device comprises a fourth block of memory cells to store a filter array and a fifth block of memory cells to store an input array, the method comprising:

executing in-place convolution of a function of the filter array over the input array to generate an array of convolved values; and

storing the array of convolved values in the first block.

18. The method of claim 17, wherein the input array and the filter array include digital values, the method comprising:

receiving the digital values as inputs to the function; and

for a set of frames of cells in the input array, convolving the filter array with each frame in the set of frames to generate the array of convolved values, where each value in the array of convolved values corresponds to a frame in the set of frames, and indicates a number of digital values from its corresponding frame that matches corresponding digital values from the filter array.

19. The method of claim 18, comprising:

applying addresses for the set of frames in the input array and the filter array to the fifth block and the fourth block in coordination with the in-place convolution.

20. The method of claim 13, comprising:

storing an analog level in each cell of the third block for the array of output values.

21. The method of claim 13, comprising:

applying a sequence of write pulses for each cell in the third block having a number of write pulses determined according to a corresponding output value in the array of output values.

22. The method of claim 13, comprising:

applying a sequence of write pulses for each cell in the third block having a pulse duration determined according to a corresponding output value in the array of output values.

23. The method of claim 13, comprising:

applying a sequence of write pulses for each cell in the third block having a tail length of a write pulse determined according to a corresponding output value in the array of output values.