In-memory convolution for machine learning
First Claim
Patent Images
1. A device, comprising:
- a first block of memory cells;
a second block of memory cells to store a feature array;
a third block of memory cells to store an array of output values at analog levels;
sensing circuitry coupled to the first block of memory cells and the second block of memory cells to compare electrical differences between the memory cells in the first block and the memory cells in the second block to generate the array of output values; and
writing circuitry operatively coupled to the third block to store the array of output values in the third block of memory cells.
1 Assignment
0 Petitions
Accused Products
Abstract
A device comprises a first block of memory cells, a second block of memory cells to store a feature array, and a third block of memory cells to store an array of output values. Sensing circuitry is coupled to the first block of memory cells and the second block of memory cells to compare electrical differences between the memory cells in the first block and the memory cells in the second block to generate the array of output values. Writing circuitry is operatively coupled to the third block to store the array of output values in the third block of memory cells.
-
Citations
23 Claims
-
1. A device, comprising:
-
a first block of memory cells; a second block of memory cells to store a feature array; a third block of memory cells to store an array of output values at analog levels; sensing circuitry coupled to the first block of memory cells and the second block of memory cells to compare electrical differences between the memory cells in the first block and the memory cells in the second block to generate the array of output values; and writing circuitry operatively coupled to the third block to store the array of output values in the third block of memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A method of operating a device comprising a first block of memory cells, a second block of memory cells to store a feature array, and a third block of memory cells to store an array of output values at analog levels, the method comprising:
-
comparing electrical differences between memory cells in the first block and the memory cells in the second block to generate the array of output values; and storing the array of output values in the third block of memory cells. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
-
Specification