Nonvolatile memory devices, memory systems and methods of operating nonvolatile memory devices for processing user data

• US 10,672,479 B2
• Filed: 09/11/2018
• Issued: 06/02/2020
• Est. Priority Date: 12/19/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Taek-Soo, Park, Chan-Ik, Shin, Hyun-Sung, Chang, Sang-Hoan
• Primary Examiner(s): Bui, Tha-O H
• Application Number:
  US16/127,793
• Publication Number:
  US 20190189221A1
• Time in Patent Office: 630 Days
• Field of Search: 36518905
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 19/287 Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines; a calculation circuit configured to perform a calculation on information bits and weight bits based on a calculation window having a first size, the information bits and weight bits being included in a user data set, the memory cell array being configured to store the user data set, the calculation circuit being further configured to receive the user data set through the page buffer circuit; and a data input/output (I/O) circuit connected to the calculation circuit, wherein the calculation circuit is further configured to provide an output data set to the data I/O circuit in response to the calculation circuit completing the calculation with respect to all of the information bits and the weight bits, and wherein the output data set corresponds to a result of the completed calculation.

Claims

1. A nonvolatile memory device comprising:

a memory cell array including a plurality of nonvolatile memory cells;

a page buffer circuit connected to the memory cell array through a plurality of bit lines;

a calculation circuit configured to perform a calculation on information bits and weight bits based on a calculation window having a first size, the information bits and weight bits being included in a user data set, the memory cell array being configured to store the user data set, the calculation circuit being further configured to receive the user data set through the page buffer circuit, the calculation including performing a multiplication operation on a matrix of bits within the calculation window from among the information bits; and

a data input/output (I/O) circuit connected to the calculation circuit,

wherein the calculation circuit is further configured to provide an output data set to the data I/O circuit in response to the calculation circuit completing the calculation with respect to all of the information bits and the weight bits, and

wherein the output data set corresponds to a result of the completed calculation.

2. The nonvolatile memory device of claim 1, further comprising:

an error correction code (ECC) engine configured to,

correct at least one error bit in the information bits and the weight bits based on parity data associated with the user data set, and

provide corrected data set to the calculation circuit.

3. The nonvolatile memory device of claim 1, wherein the calculation circuit comprises:

a shift register block configured to,

divide the weight bits based on the calculation window to provide feature maps sequentially, and

divide the information bits based on a correlation between each of the feature maps and the information bits to provide activations sequentially;

a multiplication and accumulation (MAC) circuit configured to,

perform matrix-vector multiplication on each of the feature maps and each of the activations,

accumulate a result of the matrix-vector multiplication, and

provide the output data set,

the output data set being generated by completing the performance of the matrix-vector multiplication on the feature maps and the activations; and

a data buffer configured to store the output data set to provide the output data set to the data I/O circuit in response to a write enable signal.

4. The nonvolatile memory device of claim 3, wherein the shift register block comprises:

a first shift register configured to,

arrange the weight bits into the feature maps, such that the feature maps each have a P*Q matrix configuration, and

shift the weight bits such that the feature maps are output, sequentially, based on a first calculation window to output first shifted bits,

P and Q being natural numbers; and

a second shift register configured to,

arrange the information bits into the activations such that the activations correspond to a plurality of sub data sets, each having an L*L matrix configuration, based on the correlation, and

shift the information bits such that the activations are output based on a second calculation window, each having a P*Q matrix configuration, sequentially, to output second shifted bits,

L being a natural number greater than three.

5. The nonvolatile memory device of claim 4, wherein the second shift register is configured to,

shift the second calculation window in a first direction such that 2P information bits in a second direction are repeatedly selected with respect to two consecutive positions of the second calculation window until the second calculation window reaches a boundary of the activations, and

shift the second calculation window by L-P in response to the second calculation window reaching the boundary of the activations.

6. The nonvolatile memory device of claim 4, wherein the MAC circuit comprises:

a multiplication circuit configured to,

receive the first shifted bits and the second shifted bits, and

multiply information bits in one of the activations by weight bits in a corresponding one of the feature maps to provide a multiplied result as an output; and

an accumulation circuit configured to accumulate the output of the multiplication circuit to provide the output data set.

7. The nonvolatile memory device of claim 6, wherein the multiplication circuit comprises:

a first buffer configured to receive the first shifted bits to output the first shifted bits as the feature maps on based on the first calculation window;

a second buffer configured to receive the second shifted bits to output the second shifted bits as the activations based on the second calculation window; and

a multiplier configured to multiply an output of the first buffer by an output of the second buffer to provide a multiplied result as an intermediate calculation result.

8. The nonvolatile memory device of claim 7, wherein the accumulation circuit comprises:

an adder including a first input terminal and a second input terminal; and

a buffer,

wherein the adder is configured to add the intermediate calculation result of the multiplication circuit, received at the first input terminal, with an output of the buffer, received at the second input terminal, to provide an added result to the buffer, and

wherein the buffer is configured to feed-back an output of the adder to the second input terminal of the adder and configured to provide the output of the adder as the output data set in response to an output enable signal.

9. The nonvolatile memory device of claim 8, wherein the nonvolatile memory device is configured such that the buffer is reset in response to a reset signal after the buffer outputs the output data set.

10. The nonvolatile memory device of claim 3, wherein the data buffer includes a static random access memory (SRAM) device.

11. The nonvolatile memory device of claim 1, further comprising:

a control circuit configured to control the page buffer circuit, the calculation circuit and the data I/O circuit in response to a command and an address from an outside.

12. The nonvolatile memory device of claim 11, wherein the control circuit is further configured to,

generate a calculation control signal in response to the command and the address, and

control the calculation circuit by applying the calculation control signal to the calculation circuit.

13. The nonvolatile memory device of claim 12, wherein the calculation circuit comprises:

a shift register block configured to,

divide the weight bits based on the calculation window to provide feature maps sequentially, and

divide the information bits based on the feature maps to provide activations sequentially;

a multiplication and accumulation (MAC) circuit configured to,

perform matrix-vector multiplication on each of the feature maps and each of the activations,

accumulate a result of the matrix-vector multiplication, and

provide the output data set,

the output data set being generated by completing the matrix-vector multiplication on the feature maps and the activations; and

a data buffer configured to,

store the output data set, and

provide the output data set to the data I/O circuit in response to a write enable signal.

14. The nonvolatile memory device of claim 13, wherein the control circuit is configured to,

control the MAC circuit by providing an output enable signal and a reset signal to the MAC circuit, and

control an output operation of the data buffer by providing the write enable signal to the data buffer,

wherein the calculation control signal includes the write enable signal, the reset signal and the write enable signal.

15. The nonvolatile memory device of claim 1,

wherein the memory cell array includes a plurality of memory blocks, and

wherein each of the plurality of memory blocks comprises:

first memory cells coupled to a first word line; and

second memory cells coupled to a second word line,

the second memory cells being stacked on the first memory cells.

16. The nonvolatile memory device of claim 1,

wherein the memory cell array is in a first semiconductor layer, and the first semiconductor layer includes a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction that crosses the first direction, and

wherein the page buffer circuit, the calculation circuit and the data I/O circuit are in a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions such that the first semiconductor layer is on the second semiconductor layer, and

wherein the second semiconductor layer includes a substrate.

17. The nonvolatile memory device of claim 16, wherein at least some portion of the page buffer circuit and at least some portion of the calculation circuit at least partially overlap the memory cell array in the third direction.

18. A memory system comprising:

at least one nonvolatile memory device; and

a memory controller configured to control the at least one nonvolatile memory device,

wherein the at least one nonvolatile memory device includes;

a memory cell array including a plurality of nonvolatile memory cells;

a page buffer circuit connected to the memory cell array through a plurality of bit lines;

a calculation circuit configured to perform a calculation on information bits and weight bits based on a calculation window having a first size, the information bits and weight bits being included in a user data set, the memory cell array being configured to store the user data set, the calculation circuit being further configured to receive the user data set through the page buffer circuit, the calculation including performing a multiplication operation on a matrix of bits within the calculation window from among the information bits; and

a data input/output (I/O) circuit connected to the calculation circuit,

wherein the calculation circuit is further configured to provide an output data set to the data I/O circuit in response to the calculation on the information bits and the weight bits being completed, and

wherein the output data set corresponds to a result of the completed calculation.

19. The memory system of claim 18, wherein the calculation circuit comprises:

a shift register block configured to,

divide the weight bits based on the calculation window to provide feature maps sequentially, and

divide the information bits based on the feature maps to provide activations sequentially;

a multiplication and accumulation (MAC) circuit configured to,

perform matrix-vector multiplication on each of the feature maps and corresponding each of the activations,

accumulate a result of the matrix-vector multiplication, and

provide the output data set, the output data set being generated by completing the matrix-vector multiplication on the feature maps and the activations; and

a data buffer configured to store the output data set to provide the output data set to the data I/O circuit in response to a write enable signal.

20. A method of operating a nonvolatile memory device including a memory cell array having a plurality of nonvolatile memory cells, the method comprising:

providing, from the memory cell array, information bits and weight bits to a shift register block through a page buffer circuit connected to the memory cell array through a plurality of bit lines, the information bits and weight bits being included in a user data set read through the page buffer circuit;

dividing, by the shift register block, the information bits and weight bits into activations and feature maps, respectively;

performing, by a calculation circuit, matrix-vector multiplication on the activations and the feature maps based on a calculation window; and

providing an output data set in response to the calculation circuit completing the matrix-vector multiplication with respect to all of the activations and the feature maps, the output data set corresponding to a result of the completed matrix-vector multiplication.