Semiconductor memory device

• US 10,672,482 B2
• Filed: 12/18/2019
• Issued: 06/02/2020
• Est. Priority Date: 09/06/2012
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Tokiwa, Naoya
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US16/719,585
• Publication Number:
  US 20200126626A1
• Time in Patent Office: 167 Days
• Field of Search: 36518529, 36518522, 36518517
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations.

Claims

1. A semiconductor memory device comprising:

a memory block including a first memory string and a second memory string,

the first memory string including a first selection transistor, a first memory cell, and a second memory cell, and

the second memory string including a second selection transistor, a third memory cell, and a fourth memory cell;

a first bit line connected to the first memory string and the second memory string;

a first select gate line connected to a gate of the first selection transistor;

a second select gate line connected to a gate of the second selection transistor;

a first word line connected to a gate of the first memory cell and a gate of the third memory cell;

a second word line connected to a gate of the second memory cell and a gate of the fourth memory cell; and

a controller configured to

perform an erase operation on the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell;

after the erase operation, perform a first verify operation on the first memory cell with a first verify voltage applied to the first word line and on the second memory cell with a second verify voltage applied to the second word line; and

after the first verify operation, perform a second verify operation on the third memory cell with the first verify voltage applied to the first word line kept un-discharged from a time of the first verify operation and on the fourth memory cell with the second verify voltage applied to at the second word line kept un-discharged from the time of the first verify operation.

2. The semiconductor memory device of claim 1, further comprising:

a sense amplifier connected to the first bit line,

wherein the controller is configured to apply an enable signal to the sense amplifier at least twice during the first verify operation and the second verify operation.

3. The semiconductor memory device of claim 2, wherein the sense amplifier includes a logic circuit configured to determine whether the first memory string passed or failed the first verify operation and whether the second memory string passed or failed the second verify operation.

4. The semiconductor memory device of claim 3, wherein the controller includes a first cache configured to store results of the first verify operation and the second verify operation, and the sense amplifier includes a second cache configured to store a determination result of the logic circuit.

5. The semiconductor memory device of claim 1, further comprising:

the controller is configured to store results of the first verify operation and the second verify operation in a cumulative manner.

6. The semiconductor memory device of claim 5, wherein

the controller is configured to suspend the first verify operation and the second verify operation when a cumulative number of failures is greater than or equal to a given number.

7. The semiconductor memory device of claim 1, wherein

each of the first verify operation and the second verify operation includes multiple loops of a sequence of sub verify operations performed for a corresponding one of the first memory string and the second memory string.

8. A semiconductor memory device comprising:

a memory block including first, second, third, fourth, fifth, sixth, seventh, and eighth memory strings,

the first memory string including a first selection transistor, a first memory cell, and a second memory cell,

the second memory string including a second selection transistor, a third memory cell, and a fourth memory cell,

the third memory string including a third selection transistor, a fifth memory cell, and a sixth memory cell,

the fourth memory string including a fourth selection transistor, a seventh memory cell, and an eighth memory cell,

the fifth memory string including a fifth selection transistor, a ninth memory cell, and a tenth memory cell,

the sixth memory string including a sixth selection transistor, an eleventh memory cell, and a twelfth memory cell,

the seventh memory string including a seventh selection transistor, a thirteenth memory cell, and a fourteenth memory cell, and

the eighth memory string including an eighth selection transistor, a fifteenth memory cell, and a sixteenth memory cell;

a first bit line connected to the first, second, third, fourth, fifth, sixth, seventh, and eighth memory strings;

a first select gate line connected to a gate of the first selection transistor;

a second select gate line connected to a gate of the second selection transistor;

a third select gate line connected to a gate of the third selection transistor;

a fourth select gate line connected to a gate of the fourth selection transistor;

a fifth select gate line connected to a gate of the fifth selection transistor;

a sixth select gate line connected to a gate of the sixth selection transistor;

a seventh select gate line connected to a gate of the seventh selection transistor;

an eighth select gate line connected to a gate of the eighth selection transistor;

a first word line connected to gates of the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteenth memory cells;

a second word line connected to gates of the second, fourth, sixth, eighth, tenth, twelfth, fourteenth, and sixteenth memory cells; and

a controller configured to

perform an erase operation on the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, and sixteenth memory cells;

after the erase operation, perform a first verify operation on the first memory cell with a first verify voltage applied to the first word line and on the second memory cell with a second verify voltage applied to the second word line;

after the first verify operation, perform a second verify operation on the third memory cell with the first verify voltage applied to the first word line unchanged and on the fourth memory cell with the second verify voltage applied to the second word line unchanged;

after the second verify operation, perform a third verify operation on the fifth memory cell with the first verify voltage applied to the first word line unchanged and on the sixth memory cell with the second verify voltage applied to the second word line unchanged;

after the third verify operation, perform a fourth verify operation on the seventh memory cell with the first verify voltage applied to the first word line unchanged and on the eighth memory cell with the second verify voltage applied to the second word line unchanged;

after the fourth verify operation, perform a fifth verify operation on the ninth memory cell with the first verify voltage applied to the first word line unchanged and on the tenth memory cell with the second verify voltage applied to the second word line unchanged;

after the fifth verify operation, perform a sixth verify operation on the eleventh memory cell with the first verify voltage applied to the first word line unchanged and on the twelfth memory cell with the second verify voltage applied to the second word line unchanged;

after the sixth verify operation, perform a seventh verify operation on the thirteenth memory cell with the first verify voltage applied to the first word line unchanged and on the fourteenth memory cell with the second verify voltage applied to the second word line unchanged; and

after the seventh verify operation, perform an eighth verify operation on the fifteenth memory cell with the first verify voltage applied to the first word line unchanged and on the sixteenth memory cell with the second verify voltage applied to the second word line unchanged.

9. The semiconductor memory device of claim 8, further comprising:

a sense amplifier connected to the first bit line,

wherein the controller is configured to apply an enable signal to the sense amplifier at least twice during the first verify operation and the second verify operations.

10. The semiconductor memory device of claim 9, wherein the sense amplifier includes a logic circuit configured to determine whether the first memory string passed or failed the first verify operation and whether the second memory string passed or failed the second verify operation.

11. The semiconductor memory device of claim 10, wherein the controller includes a first cache configured to store results of the first verify operation and the second verify operation, and the sense amplifier includes a second cache configured to store a determination result of the logic circuit.

12. The semiconductor memory device of claim 8, wherein

the controller is configured to store results of the first verify operation and the second verify operation in a cumulative manner.

13. The semiconductor memory device of claim 12, wherein

the controller is configured to suspend the first verify operation and the second verify operation when a cumulative number of failures is greater than or equal to a given number.

14. The semiconductor memory device of claim 8, wherein

each of the first verify operation and the second verify operation includes multiple loops of a sequence of sub verify operations performed for a corresponding one of the first, second, third, fourth, fifth, sixth, seventh, and eighth memory strings.