×

Semiconductor memory device

  • US 10,672,487 B2
  • Filed: 07/01/2019
  • Issued: 06/02/2020
  • Est. Priority Date: 12/17/2015
  • Status: Active Grant
First Claim
Patent Images

1. A semiconductor memory device comprising:

  • first, second, and third memory cells, each of which includes a charge storage layer;

    a first bit line that is connected to the first memory cell;

    a second bit line that is connected to the second memory cell;

    a third bit line that is connected to the third memory cell;

    a first sense amplifier that applies a voltage to the first bit line;

    a second sense amplifier that applies the voltage to the second bit line; and

    a third sense amplifier that applies the voltage to the third bit line, whereina writing operation includes multiple loops of a programming operation and a verification operation, andin one of the loops of the writing operation, during a programming operation, using the first sense amplifier, a first voltage is applied to the first bit line, using the second sense amplifier, a second voltage lower than the first voltage is applied to the second bit line, and using the third sense amplifier, a third voltage lower than the first voltage and higher than the second voltage is applied to the third bit line, whereinthe second voltage is applied by the second sense amplifier to the second bit line in a first loop of the writing operation,the third voltage is applied by the second sense amplifier to the second bit line in a second loop of the writing operation to be executed before the first loop, andthe first voltage is applied by the second sense amplifier to the second bit line in a third loop of the writing operation to be executed after the first loop.

View all claims
  • 3 Assignments
Timeline View
Assignment View
    ×
    ×