Semiconductor memory device

• US 10,672,487 B2
• Filed: 07/01/2019
• Issued: 06/02/2020
• Est. Priority Date: 12/17/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Maejima, Hiroshi, Hosono, Koji, Yasufuku, Tadashi, Shibata, Noboru
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US16/459,528
• Publication Number:
  US 20190325973A1
• Time in Patent Office: 337 Days
• Field of Search: 36518503
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.

Claims

1. A semiconductor memory device comprising:

first, second, and third memory cells, each of which includes a charge storage layer;

a first bit line that is connected to the first memory cell;

a second bit line that is connected to the second memory cell;

a third bit line that is connected to the third memory cell;

a first sense amplifier that applies a voltage to the first bit line;

a second sense amplifier that applies the voltage to the second bit line; and

a third sense amplifier that applies the voltage to the third bit line, wherein

a writing operation includes multiple loops of a programming operation and a verification operation, and

in one of the loops of the writing operation, during a programming operation, using the first sense amplifier, a first voltage is applied to the first bit line, using the second sense amplifier, a second voltage lower than the first voltage is applied to the second bit line, and using the third sense amplifier, a third voltage lower than the first voltage and higher than the second voltage is applied to the third bit line, wherein

the second voltage is applied by the second sense amplifier to the second bit line in a first loop of the writing operation,

the third voltage is applied by the second sense amplifier to the second bit line in a second loop of the writing operation to be executed before the first loop, and

the first voltage is applied by the second sense amplifier to the second bit line in a third loop of the writing operation to be executed after the first loop.

2. The device according to claim 1, wherein

the first voltage is applied by the sense amplifier to the second bit line in a plurality of consecutive loops of the writing operation to be executed before the first loop.

3. The device according to claim 1, wherein the first loop is a loop of the writing operation occurring directly after verification that data written in the second memory cell has passed.

4. The device according to claim 3, wherein

the third voltage is applied by the sense amplifier to the second bit line in a plurality of consecutive loops of the writing operation to be executed after the first loop.

5. The device according to claim 1, wherein the first, second, and third memory cells are configured to store multi-bit data.

6. The device according to claim 5, wherein target threshold voltages of programming operations remain the same or increase with each successive loop of the writing operation.